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HC705JJ7GRS/D 数据表(PDF) 91 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 91 Page - NXP Semiconductors

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Parallel Input/Output
Port B
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Parallel Input/Output
Table 7-2. Port B Pin Functions — PB0:4
Port B
Pin
Control Bits
PORTB Access
(Pin or Data
Register)
Result on
Port B Pins
Comparator 1
Timer
SWPDI
in
MOR
Port B
CMP1
COE1
OPT in
MOR
OLVL
PDIBx
DDRBx*
Read
Write
Pulldown
Pin
PB0
PB1
PB2
PB3
XXXX
0
0
0
Pin
Data
On
PBx In
0
1
0
Pin
Data
Off
PBx In
1
X
0
Pin
Data
Off
PBx In
X
X
1
Data
Data
Off
PBx Out
PB4
XXXX
0
0
0
Pin
Data
On
PB4 In
0
1
0
Pin
Data
Off
PB4 In
1
X
0
Pin
Data
Off
PB4 In
X
X
0
0
X
X
1
Data
Data
Off
PB4 Out
X
0
1
0
X
X
1
Data
Data
Off
PB4 Out
0110
X
X
1
Data
Data
Off
PB4 Out
X
X
X
1
X
X
1
1
Data
Off
1
1
1
1
X
X
X
1
1
Data
Off
1
* DDRB can always be read or written.
X = Don’t Care
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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