数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

HC705JJ7GRS/D 数据表(PDF) 58 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 58 Page - NXP Semiconductors

Back Button HC705JJ7GRS/D Datasheet HTML 54Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 55Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 56Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 57Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 58Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 59Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 60Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 61Page - NXP Semiconductors HC705JJ7GRS/D Datasheet HTML 62Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 58 / 230 page
background image
Interrupts
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Interrupts
4.10 Analog Interrupts
The analog subsystem can generate the following interrupts:
Voltage on positive input of comparator 1 is greater than the
voltage on the negative input of comparator 1
Voltage on positive input of comparator 2 is greater than the
voltage on the negative input of comparator 2
Trigger of the input capture interrupt from the programmable timer
as described in 4.8.1 Input Capture Interrupt.
Setting the I bit in the condition code register disables analog subsystem
interrupts. The controls for these interrupts are in the analog subsystem
control register (ACR) located at $001D, and the status bits are in the
analog subsystem status register (ASR) located at $001E.
4.10.1 Comparator Input Match Interrupt
A comparator input match interrupt occurs if either compare flag bit
(CPF1 or CPF2) in the ASR becomes set while the comparator interrupt
enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits
can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits
in the ASR. Reset clears these bits.
4.10.2 Input Capture Interrupt
The analog subsystem can also generate an input capture interrupt
through the 16-bit programmable timer. The input capture can be
triggered when there is a match in the input conditions for the voltage
comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the
input capture enable (ICEN) in the ACR is set, then an input capture will
be performed by the programmable timer. If the ICIE enable bit in the
TCR is also set, then an input compare interrupt will occur. Reset clears
these bits.
NOTE:
For the analog subsystem to generate an interrupt using the input
capture function of the programmable timer, the ICEN enable bit in the
ACR, and the ICIE and IEDG bits in the TCR must all be set.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com