HC705JJ7GRSSLASHD datasheet(86/230 Pages) NXP

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Parallel Input/Output

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Parallel Input/Output

7.4.3 Pulldown Register B (PDRB)

All port B pins can have software programmable pulldown devices

enabled or disabled globally by the SWPDI bit in the MOR. These

pulldown devices are individually controlled by the write-only pulldown

in the PDRB turns on the pulldown devices if the port B pin is an input.

Reading the PDRB returns undefined results since it is a write-only

B pulldown devices.

PDIB7–PDIB0 — Port B Pulldown Inhibit Bits

Writing to these write-only bits controls the port B pulldown devices.

Reading these pulldown register B bits returns undefined data. Reset

clears bits PDIB7–PDIB0.

1 = Corresponding port B pin pulldown device turned off

0 = Corresponding port B pin pulldown device turned on if pin has

been programmed by the DDRB to be an input

7.4.4 Port B Logic

All port B pins have the general I/O port logic similar to port A; but they

also share this function with inputs or outputs from other modules, which

are also attached to the pin itself or override the general I/O function.

PB0, PB1, PB2, and PB3 simply share their inputs with another module.

PB4, PB5, PB6, and PB7 will have their operation altered by outputs or

controls from other modules.

$0011

Bit 7

654321

Bit 0

Read:

Write:

PDIB7

PDIB6

PDIB5

PDIB4

PDIB3

PDIB2

PDIB1

DIB0

Reset:

00000000

= Unimplemented

Figure 7-7. Pulldown Register B (PDRB)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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