HC705JJ7GRSSLASHD datasheet(81/230 Pages) NXP

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Parallel Input/Output

Port A

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

7.3.3 Pulldown Register A (PDRA)

All port A pins can have software programmable pulldown devices

enabled or disabled globally by SWPDI bit in the MOR. These pulldown

devices are controlled by the write-only pulldown register A (PDRA)

shown in Figure 7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns

on the pulldown devices if the port A pin is an input. Reading the PDRA

returns undefined results since it is a write-only register, therefore do not

change the value in PDRA with read/modify/write instructions. On the

MC68HC705JP7 the PDRA contains two pulldown control bits (PDICH

and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH and

PDICL bits, which turns on all the port A and port C pulldown devices.

PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)

Writing to this write-only bit controls the port C pulldown devices on

the upper four bits (PC4:7). Reading these pulldown register A bits

returns undefined data. Reset clears bit PDICH.

1 = Upper four port C pins pulldown devices turned off

0 = Upper four port C pins pulldown devices turned on if pin has

been programmed by the DDRC to be an input

PDICL — Lower Port C Pulldown Inhibit Bits (MC68HC705JP7)

Writing to this write-only bit controls the port C pulldown devices on

the lower four bits (PC0:3). Reading these pulldown register A bits

returns undefined data. Reset clears bit PDICL.

1 = Lower four port C pins pulldown devices turned off

0 = Lower four port C pins pulldown devices turned on if pin has

been programmed by the DDRC to be an input

$0010

Bit 7

654321

Bit 0

Read:

Write:

PDICH

PDICL

PDIA5

PDIA4

PDIA3

PDIA2

PDIA1

PDIA0

Reset:

00000000

= Unimplemented

Figure 7-3. Pulldown Register A (PDRA)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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