HC705JJ7GRSSLASHD datasheet(85/230 Pages) NXP

部件名	HC705JJ7GRS/D

功能描述	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

标志

85 / 230 page

Parallel Input/Output

Port B

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

7.4.2 Data Direction Register B (DDRB)

The contents of the port B data direction register (DDRB) determine

whether each port B pin is an input or an output. Writing a logic one to a

DDRB bit enables the output buffer for the associated port B pin. A

DDRB bit set to a logic one also disables the pulldown device for that pin.

Writing a logic zero to a DDRB bit disables the output buffer for the

associated port B pin. A reset initializes all DDRB bits to logic zeros,

configuring all port B pins as inputs.

DDRB7–DDRB0 — Port B Data Direction Bits

These read/write bits control port B data direction. Reset clears the

bits DDRB7–DDRB0.

1 = Corresponding port B pin conﬁgured as output and pulldown

device disabled

0 = Corresponding port B pin conﬁgured as input

$0005

Bit 7

654321

Bit 0

Read:

DDRB7

DDRB6

DDRB5

DDRB4

DDRB3

DDRB2

DDRB1

DDRB0

Write:

Reset:

00000000

Figure 7-6. Data Direction Register B (DDRB)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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