HC705JJ7GRSSLASHD datasheet(79/230 Pages) NXP

部件名	HC705JJ7GRS/D

功能描述	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

标志

79 / 230 page

Parallel Input/Output

Port A

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Parallel Input/Output

7.3.1 Port A Data Register (PORTA)

The port A data register contains a bit for each of the port A pins. When

a port A pin is programmed to be an output, the state of its data register

bit determines the state of the output pin. When a port A pin is

programmed to be an input, reading the port A data register returns the

logic state of the pin. The upper two bits of the port A data register will

always read as logical zeros.

PA5–PA0 — Port A Data Bits

These read/write bits are software programmable. Data direction of

each bit is under the control of the corresponding bit in the port A data

direction register (DDRA). Reset has no effect on port A data.

$0000

Bit 7

654321

Bit 0

Read:

PA5

PA4

PA3

PA2

PA1

PA0

Write:

Reset:

Unaffected by Reset

Alternate:

KYBD3

KYBD2

KYBD1

KYBD0

= Unimplemented

Figure 7-1. Port A Data Register (PORTA)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 数据表(PDF) 79 Page - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载