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HC705JJ7GRS/D 数据表(PDF) 98 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 98 Page - NXP Semiconductors

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Parallel Input/Output
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
Table 7-3. Port B Pin Functions — PB5:7
Port B
Pin
Control Bits
PORTB Access
(Pin or Data
Register)
Result on
Port B Pins
SIOP
SWPDI
in
MOR
Port B
SPE
MSTR
PDIBx
DDRBx*
Read
Write
Pulldown
Pin
PB5
0X
0
0
0
Pin
Data
On
PB5 In
0
1
0
Pin
Data
Off
PB5 In
1
X
0
Pin
Data
Off
PB5 In
X
X
1
Data
Data
Off
PB5 Out
1X
X
X
0
SDO
Data
Off
SDO Out
1
Data
Data
Off
SDO Out
PB6
0X
0
0
0
Pin
Data
On
PB6 In
0
1
0
Pin
Data
Off
PB6 In
1
X
0
Pin
Data
Off
PB6 In
X
X
1
Data
Data
Off
PB6 Out
1X
X
X
0
SDI
Data
Off
SDI In
1
Data
Data
Off
SDI In
PB7
0X
0
0
0
Pin
Data
On
PB7 In
0
1
0
Pin
Data
Off
PB7 In
1
X
0
Pin
Data
Off
PB7 In
X
X
1
Data
Data
Off
PB7 Out
1
0X
X
0
SCK
Data
Off
SCK In
1
Data
Data
Off
SCK In
1X
X
0
SCK
Data
Off
SCK Out
1
Data
Data
Off
SCK Out
* DDRB can always be read or written.
X = Don’t Care
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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