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HC705JJ7GRS/D 数据表(PDF) 102 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 102 Page - NXP Semiconductors |
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102 / 230 page ![]() Parallel Input/Output General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Parallel Input/Output 7.6 Port Transitions Glitches and temporary floating inputs can occur if the control bits regarding each port I/O pin are not performed in the correct sequence. • Do not use read-modify-write instructions on pulldown register A or B. • Avoid glitches on port pins by writing to the port data register before changing data direction register bits from a logic zero to a logic one. • Avoid a floating port input by clearing its pulldown register bit before changing its data direction register bit from a logic one to a logic zero. • The SWPDI bit in the MOR turns off all port pulldown devices and disables software control of the pulldown devices. Reset has no effect on the pulldown devices when the SWPDI bit is set. • Two or more output pins of the same port can be connected electrically so as to provide output currents up to the sum of the maximum specified drive currents as defined in 15.8 DC Electrical Characteristics (5.0 Vdc) and 15.9 DC Electrical Characteristics (3.0 Vdc). Care must be taken to assure that all ganged pins always maintain the same output logic value. Table 7-4. Port C Pin Functions (28-Pin Versions Only) Port C Pin(s) Control Bits PORTC Access (Pin or Data Register) Result on Port C Pins SWPDI (in MOR) Port C PDICH PDICL DDRCx* Read Write Pulldown Pin PC0 PC1 PC2 PC3 0 X 0 0 Pin Data On PCx In 0 X 1 0 Pin Data Off PCx In 1 X X 0 Pin Data Off PCx In X X X 1 Data Data Off PCx Out PC4 PC5 PC6 PC7 0 0 X 0 Pin Data On PCx In 0 1 X 0 Pin Data Off PCx In 1 X X 0 Pin Data Off PCx In X X X 1 Data Data Off PCx Out * DDRC can always be read or written. X = Don’t care Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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