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HC705JJ7GRS/D 数据表(PDF) 105 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 105 Page - NXP Semiconductors |
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105 / 230 page  Analog Subsystem Introduction MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Analog Subsystem Figure 8-1. Analog Subsystem Block Diagram ANALOG INTERRUPT PB0 VDD AN0 CHARGE CURRENT CHG - + PB1 AN1 VDD PB2 AN2 PB3 AN3 PB4 AN4 INV COMP2 PORTB LOGIC MUX4 MUX3 MUX1 MUX2 SAMPLE PORTB LOGIC PORTB LOGIC PORTB LOGIC PORTB LOGIC ICHG HOLD INV DHOLD VREF MUX4 MUX3 MUX2 MUX1 IDISCHG 2 TO 1 MUX TCAP CMP2 CMP1 CAP TCAP TCMP MUX4 MUX3 MUX2 CP1EN MUX1 VREF ISEN CP2EN ICEN CPIE CP1EN CP2EN CPF1 CPF2 PB3/AN3/TCAP - + INV COMP1 ATD2 ATD1 CONTROL LOGIC VDD TEMPERATURE DIODE INTERNAL VREF VSS DENOTES INTERNAL ANALOG VSS VSS + - VAOFF $001D $001E $0003 VOFF OPT (MOR) 100 MV OFFSET PORT B CONTROL COE1 OPT LOGIC OLVL Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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