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HC705JJ7GRS/D 数据表(PDF) 107 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 107 Page - NXP Semiconductors |
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107 / 230 page ![]() Analog Subsystem Analog Multiplex Register MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Analog Subsystem Figure 8-3. Comparator 2 Input Circuit - + COMP2 SAMPLE HOLD DHOLD CAP TEMPERATURE DIODE INTERNAL VOFF VSS OFFSET OPT (MOR) CHANNEL PB0 SELECTION BUS VDD Table 8-1 Comparator 2 Input Sources Case HOLD (AMUX) DHOLD (AMUX) OPT (MOR) VOFF (ASR) Voltage Offset Source To Negative Input of Comparator 2 Hold Sample Voltage 00 0X No Sample capacitor connected to comparator 2 negative input; very low leakage current. 10 11 Yes Sample capacitor connected to comparator 2 negative input; bottom of capacitor offset from VSS by approximately 100 mV, very low leakage current. Divided Input 01 X X No Signal on channel selection bus is divided by 2 and connected to sample capacitor and comparator 2 negative input Direct Input 10 X X No Signal on channel selection bus is connected directly to sample capacitor and comparator 2 negative input. Internal Temperature Diode 11 X X No Internal temperature sensing diode connected directly to sample capacitor and comparator 2 negative input. X = Don’t Care Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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