HC705JJ7GRSSLASHD datasheet(109/230 Pages) NXP

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Analog Subsystem

Analog Multiplex Register

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Analog Subsystem

NOTE:

Either comparator may generate an output flag when the inputs are

exchanged due to a change in the state of the INV bit. It is therefore

recommended that the INV bit not be changed while waiting for a

comparator flag. Further, any changes to the state of the INV bit should

be followed by writing a logical one to both the CPFR1 and CPFR2 bits

to clear any extraneous CPF1 or CPF2 flags that may have occurred.

VREF

This read/write bit connects the channel select bus to VDD for making

a reference voltage measurement. It cannot be selected if any of the

other input sources to the channel select bus are selected as shown

in Table 8-2. This bit is cleared by a reset of the device.

1 = Channel select bus connected to VDD if all MUX1:4 are cleared.

0 = Channel select bus cannot be connected to VDD.

MUX1:4

These are read/write bits that connect the analog subsystem pins to

the channel select bus and voltage comparator 2 for purposes of

making a voltage measurement. They can be selected individually or

combined with any of the other input sources to the channel select

bus as shown in Table 8-2.

NOTE:

The VAOFF voltage source shown in Figure 8-1 depicts a small offset

voltage generated by the total chip current passing through the package

bond wires and lead frame that are attached to the single VSS pin. This

offset raises the internal VSS reference (AVSS) in the analog subsystem

with respect to the external VSS pin. Turning on the VSS MUX to the

channel select bus connects it to this internal AVSS reference line.

When making A/D conversions this AVSS offset gets placed on the

external ramping capacitor since the discharge device on the PB0/AN0

pin discharges the external capacitor to the internal AVSS line. Under

these circumstances the positive input (+) to comparator 2 will always be

higher than the negative input (–) until the negative input reaches the

AVSS offset voltage plus any offset in comparator 2.

Therefore, input voltages cannot be resolved if they are less than the

sum of the AVSS offset and the comparator offset, because they will

always yield a low output from the comparator.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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