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HC705JJ7GRS/D 数据表(PDF) 112 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 112 Page - NXP Semiconductors |
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112 / 230 page  Analog Subsystem General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Analog Subsystem Table 8-3. A/D Conversion Options A/D Option Mode Charge Control A/D Options Current Flow To/From PB0/AN0 ISEN ATD2 ATD1 CHG Disabled Current Source and Discharge Disabled 0 X X X Current control disabled, no source or sink current 0 Manual Charge and Discharge 1000 Begin sinking current when the CHG bit is cleared and continue to sink current until the CHG bit is set. 1001 Begin sourcing current when the CHG bit is set and continue to source current until the CHG bit is cleared. 1 Manual Charge and Automatic Discharge 1010 Begin sinking current when the CHG bit is cleared and continue to sink current until the CHG bit is set. (The CHG bit is cleared by writing a logical zero to it or when the CPF2 flag bit is set.) 1011 Begin sourcing current when the CHG bit is set; and continue to source current until the CHG bit is cleared. (The CHG bit is set by writing a logical one to it or cleared when the CPF2 flag bit is set.) 2 Automatic Charge and Discharge (TOF–ICF) Synchronized to Timer 1100 The CHG bit remains cleared until the next timer TOF occurs. 1101 The CHG bit remains set until the next timer ICF occurs. 3 Automatic Charge and Discharge (OCF–ICF) Synchronized to Timer 1110 The CHG bit remains cleared until the next timer OCF occurs. 1111 The CHG bit remains set until the next timer ICF occurs. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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