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HC705JJ7GRS/D 数据表(PDF) 70 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 70 Page - NXP Semiconductors |
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70 / 230 page  Operating Modes General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Operating Modes 6.3 Oscillator Source The MCU can be clocked by either an internal low-power oscillator (LPO) without external components or by an external pin oscillator (EPO) which uses external components. The enable and selection of the clock source is determined by the state of the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR) as shown in Figure 6-1. IRQE — External Interrupt Request Enable This read/write bit enables external interrupts. Refer to Section 4. Interrupts for more details. OM1 and OM2 — Oscillator Selects These bits control the selection and enabling of the oscillator source for the MCU. One choice is the internal LPO and the other oscillator is the EPO which is common to most MC68HC05 MCU devices. The EPO uses external components like filter capacitors and a crystal or ceramic resonator and consumes more power than the LPO. The selection and enable conditions for these two oscillators are shown in Table 6-1. Reset clears OM1 and sets OM2, which selects the LPO and disables the EPO. . $000D Bit 7 654321 Bit 0 Read: IRQE OM2 OM1 0 IRQF 0 0 0 Write: R IRQR Reset: 11000000 = Unimplemented R = Reserved Figure 6-1. IRQ Status and Control Register (ISCR) Table 6-1. Oscillator Selection OM2 OM1 Oscillator Selected Internal Low-Power Oscillator (LPO) External Pin Oscillator (EPO) Power Consumption 0 0 Internal Enabled Disabled Lowest 0 1 External Disabled Enabled Normal 1 0 Internal Enabled Disabled Lowest 1 1 Internal Enabled Enabled Normal Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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