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HC705JJ7GRS/D 数据表(PDF) 88 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 88 Page - NXP Semiconductors

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Parallel Input/Output
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
The PB0:3 pins share their inputs with another module. When using the
other attached module, the following conditions must be observed:
1. If the DDRB configures the pin as an output, then the port data
register can provide an output which may conflict with any external
input source to the other module. The pulldown device will be
disabled in this case.
2. If the DDRB configures the pin as an input, then reading the port
data register will return the state of the input in terms of the digital
threshold for that pin (analog inputs will default to logic states).
3. If DDRB configures the pin as an input and the pulldown device is
activated for a pin, it will also load the input to the other module.
4. If interaction between the port logic and the other module is not
desired, the pin should be configured as an input by clearing the
appropriate DDRB bit. The input pulldown device is disabled by
clearing the appropriate PDRB bit (or by disabling programmable
pulldowns with the SWPDI bit in the MOR).
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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