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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HC705JJ7GRS/D 数据表(PDF) 48 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 48 Page - NXP Semiconductors |
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48 / 230 page  Interrupts General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Interrupts 4.4 Interrupt Processing The CPU does the following actions to begin servicing an interrupt: • Stores the CPU registers on the stack in the order shown in Figure 4-1 • Sets the I bit in the condition code register to prevent further interrupts • Loads the program counter with the contents of the appropriate interrupt vector locations as shown in Table 4-1 The return from interrupt (RTI) instruction causes the CPU to recover its register contents from the stack as shown in Figure 4-1. The sequence of events caused by an interrupt is shown in the flow chart in Figure 4-2. $0020 (Bottom of RAM) $0021 $00BE $00BF $00C0 (Bottom of Stack) $00C1 $00C2 Unstacking Order ⇓ n Condition Code Register 5 1 n+1 Accumulator 4 2 n+2 Index Register 3 3 n+3 Program Counter (High Byte) 2 4 n+4 Program Counter (Low Byte) 1 5 ⇑ Stacking $00FD Order $00FE $00FF Top of Stack (RAM) Figure 4-1. Interrupt Stacking Order Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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