HC705JJ7GRSSLASHD datasheet(78/230 Pages) NXP

部件名	HC705JJ7GRS/D

功能描述	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

标志

78 / 230 page

Parallel Input/Output

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Parallel Input/Output

7.2 Introduction

The MC68HC705JJ7 has 14 bidirectional I/O pins which form two

parallel I/O ports, A and B. The MC68HC705JP7 has 22 bidirectional I/O

pins which form three parallel I/O ports, A, B and C. Each I/O pin is

programmable as an input or an output. The contents of the data

direction registers determine the data direction of each of the I/O pins.

All I/O pins have software programmable pulldown devices which can be

enabled or disabled globally by the SWPDI bit in the mask option register

(MOR).

7.3 Port A

Port A is a 6-bit, general-purpose bidirectional I/O port with these

features:

•

Individual programmable pulldown devices

•

High current sinking capability on all port A pins, with a maximum

total for port A

•

High current sourcing capability on all port A pins, with a maximum

total for port A

•

External interrupt capability (pins PA3–PA0)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 数据表(PDF) 78 Page - NXP Semiconductors