HC705JJ7GRSSLASHD datasheet(80/230 Pages) NXP

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Parallel Input/Output

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Parallel Input/Output

7.3.2 Data Direction Register A (DDRA)

The contents of the port A data direction register (DDRA) determine

whether each port A pin is an input or an output. Writing a logic one to a

DDRA bit enables the output buffer for the associated port A pin. A

DDRA bit set to a logic one also disables the pulldown device for that pin.

Writing a logic zero to a DDRA bit disables the output buffer for the

associated port A pin. The upper two bits always read as logical zeros.

A reset initializes all DDRA bits to logic zeros, configuring all port A pins

as inputs and disabling the voltage comparators from driving PA4 or

PA5.

DDRA5–DDRA0 — Port A Data Direction Bits

These read/write bits control port A data direction. Reset clears the

DDRA5–DDRA0 bits.

1 = Corresponding port A pin conﬁgured as output and pulldown

device disabled

0 = Corresponding port A pin conﬁgured as input

$0004

Bit 7

654321

Bit 0

Read:

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Write:

Reset:

00000000

= Unimplemented

Figure 7-2. Data Direction Register A (DDRA)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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