ADE7878 datasheet(34/92 Pages) AD

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ADE7878

Rev. 0 | Page 34 of 92

set to 1 at the end of the period. This bit remains at 1 for the

duration of the second PEAKCYC period of four line cycles.

The maximum absolute value of Phase B is the greatest during

the second PEAKCYC period; therefore, the maximum absolute

value is written into the less significant 24 bits of the IPEAK

1 at the end of the period.

At the end of the peak detection period in the current channel,

Bit 23 (PKI) in the STATUS1[31:0] register is set to 1. If Bit 23

(PKI) in the MASK1[31:0] register is set, then the IRQ1 interrupt

pin is driven low at the end of the PEAKCYC period, and Status

Bit 23 (PKI) in the STATUS1[31:0] register is set to 1. In a

similar way, at the end of the peak detection period in the voltage

channel, Bit 24 (PKV) in the STATUS1[31:0] register is set to 1.

If Bit 24 (PKV) in the MASK1[31:0] register is set, then the

IRQ1 interrupt pin is driven low at the end of the PEAKCYC

period and Status Bit 24 (PKV) in the STATUS1[31:0] is set to 1.

To find the phase that triggered the interrupt, one of either the

IPEAK[31:0] or VPEAK[31:0] registers is read immediately after

reading the STATUS1[31:0] register. Then the status bits are

cleared and the IRQ1 pin is set to high by writing to the

STATUS1[31:0] register with the status bit set to 1.

Note that the internal zero-crossing counter is always active. By

setting Bits [4:2] (PEAKSEL[2:0]) in the MMODE[7:0] register,

the first peak detection result is not executed across a full

PEAKCYC period. Writing to the PEAKCYC[7:0] register when

the PEAKSEL[2:0] bits are set resets the zero-crossing counter,

thereby ensuring that the first peak detection result is obtained

across a full PEAKCYC period.

Overvoltage and Overcurrent Detection

The ADE7878 detects when the instantaneous absolute value

measured on the voltage and current channels becomes greater

than the thresholds set in the OVLVL[23:0] and OILVL[23:0]

24-bit unsigned registers. If Bit 18 (OV) in the MASK1[31:0]

overvoltage event. There are two status flags set when the IRQ1

interrupt pin is driven low: Bit 18 (OV) in the STATUS1[31:0]

PHSTATUS[15:0] register to identify the phase that generated

the overvoltage.

The Status Bit 18 (OV) in the STATUS1[31:0] register and all

Bits[11:9] (OVPHASE[2:0]) in the PHSTATUS[15:0] register

are cleared and the IRQ1 pin is set to high by writing to the

STATUS1[31:0] register with the status bit set to 1.

presents overvoltage detection in Phase A voltage.

Figure 49

OVLVL[23:0]

BIT 18 (OV) OF

STATUS1

BIT 9 (OVPHASE)

OF PHSTATUS

PHASE A

VOLTAGE CHANNEL

OVERVOLTAGE

DETECTED

STATUS1[18] AND

PHSTATUS[9]

CANCELLED BY A

WRITE OF STATUS1

WITH OV BIT SET.

Figure 49. Overvoltage Detection

Whenever the absolute instantaneous value of the voltage goes

above the threshold from the OVLVL[23:0] register, Bit 18 (OV)

in the STATUS1[31:0] register and Bit 9 (OVPHASE[0]) in the

PHSTATUS[15:0] register are set to 1. Bit 18 (OV) of the

STATUS1[31:0] register and Bit 9 (OVPHASE[0]) in the

PHSTATUS[15:0] register are cancelled when the STATUS1

The recommended procedure to manage overvoltage events is

the following:

Enable OV interrupts in the MASK1[31:0] register by

setting Bit 18 (OV) to 1.

When an overvoltage event happens, the IRQ1 interrupt

pin goes low.

The STATUS1[31:0] register is read with Bit 18 (OV) set to 1.

The PHSTATUS[15:0] register is read, identifying on

which phase or phases an overvoltage event happened.

The STATUS1[31:0] register is written with Bit 18 (OV) set

to 1. In this moment, Bit OV is erased as are all Bits[11:9]

(OVPHASE[2:0]) of the PHSTATUS[15:0] register.

In case of an overcurrent event, if Bit 17 (OI) in the MASK1[31:0]

Bit 17 (OI) in the STATUS1[31:0] register and one of Bits[5:3]

(OIPHASE[2:0]) in the PHSTATUS[15:0] register, which

identify the phase that generated the interrupt, are set. To find

the phase that triggered the interrupt, the PHSTATUS[15:0]

the STATUS1[31:0] register with the status bit set to 1. The

process is similar with overvoltage detection.

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