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ADE7878 数据表(PDF) 80 Page - Analog Devices

部件名 ADE7878
功能描述  Polyphase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  92 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7878 数据表(HTML) 80 Page - Analog Devices

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ADE7878
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Bit
Location
Bit Name
Default Value
Description
6
REVAPA
0
When this bit is set to 1, it enables an interrupt when the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
7
REVAPB
0
When this bit is set to 1, it enables an interrupt when the Phase B active power identified by Bit 6
(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
8
REVAPC
0
When this bit is set to 1, it enables an interrupt when the Phase C active power identified by Bit 6
(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
9
REVPSUM1
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1
datapath changes sign.
10
REVRPA
0
When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified by Bit
7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
11
REVRPB
0
When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified by
Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
12
REVRPC
0
When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified by
Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
13
REVPSUM2
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2
datapath changes sign.
14
CF1
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the CF1
pin, that is an active low pulse is generated. The interrupt can be enabled even if the CF1 output
is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE[15:0] register. The type of power used at
the CF1 pin is determined by Bits[2:0] (CF1SEL) in the CFMODE[15:0] register (see Table 39).
15
CF2
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2 pin,
that is an active low pulse is generated. The interrupt may be enabled even if the CF2 output is
disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE[15:0] register. The type of power used at
the CF2 pin is determined by Bits[5:3] (CF2SEL) in the CFMODE[15:0] register (see Table 39).
16
CF3
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3 pin,
that is an active low pulse is generated. The interrupt may be enabled even if the CF3 output is
disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE[15:0] register. The type of power used at
the CF3 pin is determined by Bits[8:6] (CF3SEL) in the CFMODE[15:0] register (see Table 39).
17
DREADY
0
When this bit is set to 1, it enables an interrupt when all periodic (at 8 kHz rate) DSP
computations finish.
18
REVPSUM3
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3
datapath changes sign.
31:19
Reserved
00 0000 0000
0000
Reserved. These bits do not manage any functionality.
Table 34. MASK1 Register (Address 0xE50B)
Bit
Location
Bit Name
Default Value
Description
0
NLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition
based on total active and reactive powers.
1
FNLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition
based on fundamental active and reactive powers.
2
VANLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition
based on apparent power.
3
ZXTOVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A voltage is
missing.
4
ZXTOVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B voltage is
missing.
5
ZXTOVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C voltage is
missing.
6
ZXTOIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A current is
missing.



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