ADE7878 datasheet(35/92 Pages) AD

35 / 92 page

ADE7878

Rev. 0 | Page 35 of 92

Overvoltage and Overcurrent Level Set

The content of the overvoltage, OVLVL[23:0], and overcurrent,

OILVL[23:0], 24-bit unsigned registers is compared to the abso-

lute value of the voltage and current channels. The maximum value

of these registers is the maximum value of the HPF outputs:

+5,928,256 (0x5A7540). When OVLVL or OILVL is equal to

this value, the overvoltage or overcurrent conditions are never

detected. Writing 0x0 to these registers signifies the overvoltage

or overcurrent conditions are continuously detected and the

corresponding interrupts are triggered permanently.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words. Similar to the register presented in

Figure 33, the OILVL and OVLVL registers are accessed as

32-bit registers with the eight MSBs padded with 0s.

Neutral Current Mismatch

In 3-phase systems, the neutral current is equal to the algebraic

sum of the phase currents: IN(t) = IA(t) + IB(t) + IC(t). If there is

a mismatch between these two quantities, then a tamper

situation may have occurred in the system.

The ADE7878 computes the sum of the phase currents, adding

the content of the IAWV[23:0], IBWV[23:0], and ICWV[23:0]

registers and storing the result into the ISUM[27:0] 28-bit

signed register: ISUM(t) = IA(t) + IB(t) + IC(t). ISUM is computed

every 125 μs (8 kHz frequency), the rate at which the current

samples are available. Bit 17 (DREADY) in the STATUS0[31:0]

read. See the Digital Signal Processor section for more details on

Bit DREADY.

To recover the ISUM(t) value from the ISUM[27:0] register, use

the following expression:

MAX

SUM

ADC

ISUM

]

[

)

(

where:

ADCMAX

= 5,928,256, the ADC output when the input is at full

scale.

IFS

= the full-scale ADC phase current.

The ADE7878 computes the difference between the absolute

values of ISUM and the neutral current from the INWV[23:0]

ISUMLVL threshold. If

ISUMLVL

INWV

ISUM

≤

−

, then it

is assumed that the neutral current is equal to the sum of the

phase currents and the system functions correctly. If

ISUMLVL

INWV

ISUM

−

, then a tamper situation may

have occurred, and Bit 20 (MISMTCH) in the STATUS1[31:0]

enabled by setting Bit 20 (MISMTCH) in the MASK1[31:0]

MISMTCH is set to 1. The status bit is cleared and the IRQ1 pin

is set back high by writing the STATUS1 register with Bit 20

(MISMTCH) set to 1.

ISUMLVL

INWV

ISUM

≤

−

, then MISMTCH = 0

ISUMLVL

INWV

ISUM

−

, then MISMTCH = 1

ISUMLVL[23:0], the positive threshold used in the process, is a

24-bit signed register. Because it is used in a comparison with

an absolute value, it should always be set as a positive number,

somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses the

same scale of the current ADCs outputs, so writing +5,928,256

(0x5A7540) to the ISUMLVL register puts the mismatch

detection level at full scale; see the Current Channel ADC

Section for details. Writing 0x000000, the default value, or a

negative value, signifies that the MISMTCH event is always

triggered. The right value for the application should be written into

the ISUMLVL[23:0] register after power-up or after a

hardware/software reset to avoid continuously triggering

MISMTCH events.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. As

presented in Figure 50, ISUM[27:0], the 28-bit signed register is

accessed as a 32-bit register with the four most significant bits

padded with 0s.

28 27

BIT 27 IS A SIGN BIT

28-BIT SIGNED NUMBER

0000

Figure 50. ISUM[27:0] Register Is Transmitted As a 32-Bit Word

Similar to the registers presented in Figure 32, the ISUMLVL[23:0]

significant bits padded with 0s and sign extended to 28 bits.

PHASE COMPENSATION

As described in the Current Channel ADC and Voltage Channel

ADC sections, the datapath for both current and voltages is the

same. The phase error between current and voltage signals

introduced by the ADE7878 is negligible. However, the ADE7878

must work with transducers that may have inherent phase

errors. For example, a current transformer (CT) with a phase

error of 0.1° to 3° is not uncommon. These phase errors can

vary from part to part, and they must be corrected to perform

accurate power calculations.

The errors associated with phase mismatch are particularly

noticeable at low power factors. TheADE7878 provides a means

of digitally calibrating these small phase errors. The ADE7878

allows a small time delay or time advance to be introduced into

the signal processing chain to compensate for the small phase

errors.

The phase calibration registers (APHCAL[9:0], BPHCAL[9:0],

and CPHCAL[9:0]) are 10-bit registers that can vary the time

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