ADE7878 datasheet(55/92 Pages) AD

55 / 92 page

ADE7878

Rev. 0 | Page 55 of 92

The line cycle apparent energy accumulation mode is activated

by setting Bit 2 (LVA) in the LCYCMODE[7:0] register. The

apparent energy accumulated over an integer number of zero

crossings is written to the xVAHR accumulation registers after

the number of zero crossings specified in the LINECYC register

is detected. When using the line cycle accumulation mode, Bit 6

(RSTREAD) of the LCYCMODE[7:0] register should be set to

Logic 0 because a read with the reset of xVAHR registers is not

available in this mode.

Phase A, Phase B, and Phase C zero crossings are, respectively,

included when counting the number of half-line cycles by

setting Bits[5:3] (ZXSEL) in the LCYCMODE[7:0] register. Any

combination of the zero crossings from all three phases can be

used for counting the zero crossing. Select only one phase at a

time for inclusion in the zero-crossings count during calibration.

For details on setting the LINECYC[15:0] register and Bit 5

(LENERGY) in the MASK0 interrupt mask register associated

with the line cycle accumulation mode, see the Line Cycle

Active Energy Accumulation Mode section.

WAVEFORM SAMPLING MODE

The waveform samples of the current and voltage waveform, the

active, reactive, and apparent power multiplier outputs are

stored every 125 μs (8 kHz rate) into 24-bit signed registers that

can be accessed through various serial ports of the ADE7878.

Table 20 provides the list of registers and their descriptions.

Table 20. Waveform Registers List

Description

IAWV

Phase A current

VAWV

Phase A voltage

IBWV

Phase B current

VBWV

Phase B voltage

ICWV

Phase C current

VCWV

Phase C voltage

INWV

Neutral current

AVA

Phase A apparent power

Description

BVA

Phase B apparent power

CVA

Phase C apparent power

AWATT

Phase A active power

BWATT

Phase B active power

CWATT

Phase C active power

AVAR

Phase A reactive power

BVAR

Phase B reactive power

CVAR

Phase C reactive power

Bit 17 (DREADY) in the STATUS0[31:0] register can be used to

signal when the registers listed in Table 20 can be read using the

I2C or SPI serial port. An interrupt attached to the flag can be

enabled by setting Bit 17 (DREADY) in the MASK0[31:0]

on Bit DREADY.

The ADE7878 contains a high speed data capture (HSDC) port

that is specially designed to provide fast access to the waveform

sample registers. Read the HSDC Interface section for more

details.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words. All registers listed in Table 20 are trans-

mitted sign extended from 24 bits to 32 bits (see Figure 34).

ENERGY-TO-FREQUENCY CONVERSION

The ADE7878 provides three frequency output pins: CF1, CF2,

and CF3. The CF3 pin is multiplexed with the HSCLK pin of

the HSDC interface. When HSDC is enabled, the CF3

functionality is disabled at the pin. The CF1 and CF2 pins are

always available. After initial calibration at manufacturing, the

manufacturer or end customer verifies the energy meter

calibration. One convenient way to verify the meter calibration

is to provide an output frequency proportional to the active,

reactive, or apparent power under steady load conditions. This

output frequency can provide a simple, single-wire, optically

isolated interface to external calibration equipment. Figure 69

illustrates the energy-to-frequency conversion in the ADE7878.

DIGITAL SIGNAL

PROCESSOR

INSTANTANEOUS

PHASE A ACTIVE

POWER

INSTANTANEOUS

PHASE B ACTIVE

POWER

INSTANTANEOUS

PHASE C ACTIVE

POWER

TERMSELx BITS IN

COMPMODE

WTHR[47:0]

FREQUENCY

DIVIDER

VAR

FWATT

FVAR

WATT

CFxSEL BITS

IN CFMODE

REVPSUMx BIT OF

STATUS0[31:0]

CFxDEN

ACCUMULATOR

CFx PULSE

OUTPUT

Figure 69. Energy-to-Frequency Conversion

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