ADE7878 datasheet(30/92 Pages) AD

30 / 92 page

ADE7878

Rev. 0 | Page 30 of 92

The digital filter has a pole at 80 Hz and is clocked at 256 kHz.

As a result, there is a phase lag between the analog input signal

(one of IA, IB, IC, VA, VB, and VC) and the output of LPF1.

The error in ZX detection is 0.0703° for 50 Hz systems (0.0843°

for 60 Hz systems). The phase lag response of LPF1 results in a

time delay of approximately 31.4° or 1.74 ms (at 50 Hz) between

its input and output. The overall delay between the zero crossing

on the analog inputs and ZX detection obtained after LPF1 is

about 39.6° or 2.2 ms (at 50 Hz). The ADC and HPF introduce

the additional delay. The LPF1 cannot be disabled to assure a

good resolution of the ZX detection. Figure 40 shows how the

zero-crossing signal is detected.

GAIN[23:0]

REFERENCE

HPFDIS

[23:0]

DSP

HPF

PGA

ADC

IA, IB, IC,

VA, VB, VC

DETECTION

LPF1

IA, IB, IC,

OR VA, VB, VC

39.6° OR 2.2ms @ 50Hz

0.855

LPF1 OUTPUT

Figure 40. Zero-Crossing Detection on Voltage and Current Channels

To provide further protection from noise, input signals to the

voltage channel with amplitude lower than 10% of full scale do not

generate zero-crossing events at all. The Current Channel ZX

detection circuit is active for all input signals independent of their

amplitudes.

The ADE7878 contains six zero-crossing detection circuits, one

for each phase voltage and current channel. Each circuit drives

one flag in the STATUS1[31:0] register. If a circuit placed in the

Phase A voltage channel detects one zero-crossing event, then

Bit 9 (ZXVA) in the STATUS1[31:0] register is set to 1.

Similarly, the Phase B voltage circuit drives Bit 10 (ZXVB), the

Phase C voltage circuit drives Bit 11 (ZXVC), and circuits placed

in the current channel drive Bit 12 (ZXIA), Bit 13 (ZXIB), and

Bit 14 (ZXIC). If a ZX detection bit is set in the MASK1[31:0]

ponding status flag is set to 1. The status bit is cleared and the

IRQ1 pin is set to high by writing to the STATUS1 register with

the status bit set to 1.

Zero-Crossing Timeout

Every zero-crossing detection circuit has an associated timeout

16-bit ZXTOUT register and is decremented (1 LSB) every

62.5 μs (16 kHz clock). The register is reset to the ZXTOUT

value every time a zero crossing is detected. The default value of

this register is 0xFFFF. If the timeout register decrements to 0

before a zero crossing is detected, then one of Bits[8:3] of the

STATUS1[31:0] register is set to 1. Bit 3 (ZXTOVA), Bit 4

(ZXTOVB), and Bit 5 (ZXTOVC) refer to Phase A, Phase B, and

Phase C of the voltage channel; Bit 6 (ZXTOIA), Bit 7

(ZXTOIB), and Bit 8 (ZXTOIC) refer to Phase A, Phase B, and

Phase C of the current channel.

If a ZXTOUT bit is set in the MASK1[31:0] register, the IRQ1

interrupt pin is driven low when the corresponding status bit is set

to 1. The status bit is cleared and the IRQ1 pin is returned to high

by writing to the STATUS1 register with the status bit set to 1.

The resolution of the ZXOUT register is 62.5 μs (16 kHz clock)

per LSB. Thus, the maximum timeout period for an interrupt is

4.096 sec: 216/16 kHz.

Figure 41 shows the mechanism of the zero-crossing timeout

detection when the voltage or the current signal stays at a fixed

dc level for more than 62.5 × ZXTOUT μs.

16-BIT INTERNAL

ZXTOUT

VOLTAGE

CURRENT

SIGNAL

IRQ1 INTERRUPT PIN

ZXZOxy FLAG IN

STATUS1[31:0], x = V, A

y = A, B, C

Figure 41. Zero-Crossing Timeout Detection

Phase Sequence Detection

TheADE7878 has an on-chip phase sequence error detection

circuit. This detection works on phase voltages and considers

only the zero crossings determined by their negative to positive

transitions. The regular succession of these zero-crossing events is

Phase A followed by Phase B followed by Phase C (see Figure 43).

If the sequence of zero-crossing events is, instead, Phase A followed

by Phase C followed by Phase B, then Bit 19 (SEQERR) in the

STATUS1[31:0] register is set.

If Bit 19 (SEQERR) in the MASK1[31:0] register is set to 1 and a

phase sequence error event is triggered, the IRQ1 interrupt pin

is driven low. The status bit is cleared and the IRQ1 pin is set

high by writing to the STATUS1 register with the Status Bit 19

(SEQERR) set to 1.

The phase sequence error detection circuit is functional only

when the ADE7878 is connected in a 3-phase, 4-wire, three voltage

sensors configuration (Bits[5:4], CONSEL in ACCMODE[7:0], set

to 00). In all other configurations, only two voltage sensors are

ADE7878 数据表(PDF) 30 Page - Analog Devices

ADE7878 数据表(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载