ADE7878 datasheet(63/92 Pages) AD

63 / 92 page

ADE7878

Rev. 0 | Page 63 of 92

JUMP

TO ISR

GLOBAL

INTERRUPT

MASK

CLEAR MCU

INTERRUPT

FLAG

READ

STATUSx

READ

PHx

JUMP

TO ISR

WRITE

BACK

STATUSx

ISR ACTION

(BASED ON STATUSx CONTENTS)

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

MCU

INTERRUPT

FLAG SET

PROGRAM

SEQUENCE

IRQx

Figure 79. Interrupt Management When PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers Is Involved

SERIAL INTERFACES

The ADE7878 have three serial port interfaces: one fully

licensed I2C interface, one serial peripheral interface (SPI), and

one high speed data capture port (HSDC). Because the SPI pins

are multiplexed with some of the pins of the I2C and HSDC

ports, the ADE7878 accepts two configurations: one using the

SPI port only and one using the I2C port in conjunction with

the HSDC port.

Serial Interface Choice

After reset, the HSDC port is always disabled. The choice

between the I2C and SPI port is done by manipulating the SS

pin after power-up or after a hardware reset. If the SS pin is kept

high, then the ADE7878 uses the I2C port until a new hardware

reset is executed. If the SS pin is toggled high to low three times

after power-up or after a hardware reset, the ADE7878 uses the

SPI port until a new hardware reset is executed. This

manipulation of the SS pin can be accomplished in two ways.

Use the SS pin of the master device (that is, the microcontroller)

as a regular I/O pin and toggle it three times, or execute three

SPI write operations to a location in the address space that is

not allocated to a specific ADE7878 register (for example

0xEBFF, where eight bit writes can be executed). These writes

allow the SS pin to toggle three times. See the

section for details on the write protocol involved.

SPI Write

Operation

After the serial port choice is completed, it must be locked so

that the active port remains in use until a hardware reset is

executed in PSM0 normal mode or until a power-down. If I2C is

the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2[7:0]

ADE7878 ignores spurious toggling of the SS pin, and an

eventual switch into using the SPI port is no longer possible. If

the SPI is the active serial port, any write to the CONFIG2[7:0]

the I2C port is no longer possible. Once locked, the serial port

choice is maintained when the ADE7878 changes PSMx power

modes.

The functionality of the ADE7878 is accessible via several on-

chip registers. The contents of these registers can be updated or

read using the I2C or SPI interface. The HSDC port provides the

state of up to 16 registers representing instantaneous values of

phase voltages and neutral currents, and active, reactive, and

apparent powers.

I2C-Compatible Interface

The ADE7878 supports a fully licensed I2C interface. The I2C

interface is implemented as a full hardware slave. SDA is the

data I/O pin, and SCL is the serial clock. These two pins are

shared with the MOSI and SCLK pins of the on-chip SPI

interface. The maximum serial clock frequency supported by

this interface is 400 kHz.

The two pins used for data transfer, SDA and SCL, are configured

in a wire-AND’ed format that allows arbitration in a multi-

master system.

The transfer sequence of an I2C system consists of a master

device initiating a transfer by generating a start condition while

the bus is idle. The master transmits the address of the slave

device and the direction of the data transfer in the initial

address transfer. If the slave acknowledges, then the data

transfer is initiated. This continues until the master issues a stop

condition and the bus becomes idle.

I2C Write Operation

The write operation using the I2C interface of the ADE7878

initiates when the master generates a start condition and

consists of one byte representing the address of the ADE7878

followed by the 16-bit address of the target register and by the

value of the register.

The most significant seven bits of the address byte constitute

the address of the ADE7878, and they are equal to 0111000b.

Bit 0 of the address byte is a read/write bit. Because this is a

write operation, it must be cleared to 0; therefore, the first byte

of the write operation is 0x70. After every byte is received, the

ADE7878 generates an acknowledge. Because registers may

have 8, 16, or 32 bits, after the last bit of the register is

transmitted and the ADE7878 acknowledges the transfer, the

master generates a stop condition. The addresses and the

for details of the I2C write operation.

Figure 80

I2C Read Operation

The read operation using the I2C interface of the ADE7878 is

accomplished in two stages. The first stage sets the pointer to

the address of the register. The second stage reads the content of

the register.

As seen in Figure 81, the first stage initiates when the master

generates a start condition and consists of one byte representing

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