ADE7878 datasheet(67/92 Pages) AD

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ADE7878

Rev. 0 | Page 67 of 92

Table 22. HSDC_CFG Register

Bit Location

Bit Name

Default Value

Description

HCLK

0: HSCLK is 8 MHz.

1: HSCLK is 4 MHz.

HSIZE

0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.

1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.

HGAP

0: no gap is introduced between packages.

1: a gap of 7 HCLK cycles is introduced between packages.

4:3

HXFER[1:0]

00 = HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV, IBWV,

VBWV, ICWV, VCWV, one 32-bit word always equal to INWV, AVA, BVA, CVA, AWATT,

BWATT, CWATT, AVAR, BVAR, and CVAR.

01 = HSDC. For the ADE7878, HSDC transmits seven instantaneous values of currents

and voltages: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, and INWV.

10 = HSDC transmits nine instantaneous values of phase powers: AVA, BVA, CVA, AWATT,

BWATT, CWATT, AVAR, BVAR, and CVAR.

11 = reserved. If set, the ADE7878 behaves as if HXFER[1:0] = 00.

HSAPOL

0: HSACTIVE output pin is active low.

1: HSACTIVE output pin is active high.

7:6

Reserved. These bits do not manage any functionality.

When HXFER[1:0] is 10, only the instantaneous values of phase

powers are transmitted in the following order: AVA, BVA, CVA,

AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR. The

Value 11 for HXFER[1:0] is reserved and writing it is equivalent

to writing 00, the default value.

Bit 5 (HSAPOL) determines the polarity of the HSA pin during

communication. When HSAPOL is 0 (the default value), the

HSA pin is active low during the communication. This means

that HSA stays high when no communication is in progress.

When the communication starts, HSA goes low and stays low

until the communication ends. Then it goes back to high. When

HSAPOL is 1, the HSA pin is active high during the communi-

cation. This means that HSA stays low when no communication

is in progress. When the communication starts, HSA goes high

and stays high until the communication ends. Then it goes back

to low.

Bits[7:6] of HSDC_CFG are reserved. Any value written into

these bits does not have any consequence on HSDC behavior.

Figure 86 shows the HSDC transfer protocol for HGAP = 0,

HXFER[1:0] = 00, and HSAPOL = 0. Note that the HSDC

interface sets a bit on the HSD line every HSCLK high-to-low

transition and that the value of Bit HSIZE is irrelevant.

Figure 87 shows the HSDC transfer protocol for HSIZE = 0,

HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the

HSDC interface introduces a seven-HSCLK cycles gap between

every 32-bit word.

Figure 88 shows the HSDC transfer protocol for HSIZE = 1,

HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the

HSDC interface introduces a seven-HSCLK cycles gap between

every 8-bit word.

Table 23 lists the time it takes to execute an HSDC data transfer

for all HSDC_CFG[7:0] settings. For some settings, the transfer

time is less than 125 μs (8 kHz), the waveform sample registers

update rate. This means that the HSDC port transmits data

every sampling cycle. For settings in which the transfer time is

greater than 125 μs, the HSDC port transmits data only in the

first of two consecutive 8 kHz sampling cycles. This means it

transmits registers at an effective rate of 4 kHz.

ADE7878 数据表(PDF) 67 Page - Analog Devices

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