ADE7878 datasheet(24/92 Pages) AD

24 / 92 page

ADE7878

Rev. 0 | Page 24 of 92

THEORY OF OPERATION

ANALOG INPUTS

The ADE7878 has seven analog inputs forming current and

voltage channels. The current channels consist of four pairs of

fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP

and ICN, and INP and INN. These voltage input pairs have a

maximum differential signal of ±0.5 V. In addition, the

maximum signal level on analog inputs for IxP/IxN is ±0.5 V

with respect to AGND. The maximum common-mode signal

allowed on the inputs is ±25 mV. Figure 24 presents a schematic

of the current channels inputs and their relation to the

maximum common-mode voltage.

All inputs have a programmable gain amplifier (PGA) with a

possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and

IC inputs is set in Bits[2:0] (PGA1) of the Gain[15:0] register.

The gain of the IN input is set in Bits[5:3] (PGA2) of the

Gain[15:0] register; thus, a different gain from the IA, IB, or IC

inputs is possible. See Table 38 for details on the Gain[15:0]

The voltage channel has three single-ended voltage inputs: VAP,

VBP, and VCP. These single-ended voltage inputs have a maximum

input voltage of ±0.5 V with respect to VN. In addition, the max-

imum signal level on analog inputs for VxP and VN is ±0.5 V

with respect to AGND. The maximum common-mode signal

allowed on the inputs is ±25 mV. Figure 26 presents a schematic

of the voltage channels inputs and their relation to the maximum

common-mode voltage.

All inputs have a programmable gain with a possible gain

selection of 1, 2, 4, 8, or 16. The setting is done using Bits[8:6]

(PGA3) in the Gain[15:0] register (see Table 38).

Figure 25 shows how the gain selection from the Gain[15:0]

IAP, IBP,

ICP OR INP

IAN, IBN,

ICN OR INN

VCM

+500mV

VCM

V1 + V2

DIFFERENTIAL INPUT

V1 + V2 = 500mV MAX PEAK

COMMON MODE

VCM = ±25mV MAX

–500mV

Figure 24. Maximum Input Level, Current Channels, Gain = 1

ANALOG-TO-DIGITAL CONVERSION

The ADE7878 has seven sigma-delta (Σ-Δ) analog-to-digital

converters (ADCs). In PSM0 mode, all ADCs are active. In

PSM1 mode, the ADCs that measure the Phase A, Phase B, and

Phase C currents only are active. The ADCs that measure the

neutral current and the A, B, and C phase voltages are turned

off. In PSM2 and PSM3 modes, the ADCs are powered down to

minimize power consumption.

For simplicity, the block diagram in Figure 27 shows a first-

order Σ-Δ ADC. The converter is made up of the Σ-Δ modulator

and the digital low-pass filter.

A Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7878, the sampling clock is equal to 1.024 MHz

(CLKIN/16). The 1-bit DAC in the feedback loop is driven by

the serial data stream. The DAC output is subtracted from the

input signal. If the loop gain is high enough, the average value

of the DAC output (and therefore the bit stream) can approach

that of the input signal level. For any given input value in a

single sampling interval, the data from the 1-bit ADC is

virtually meaningless. Only when a large number of samples is

averaged is a meaningful result obtained. This averaging is

carried out in the second part of the ADC, the digital low-pass

filter. By averaging a large number of bits from the modulator,

the low-pass filter can produce 24-bit data-words that are

proportional to the input signal level.

K × VIN

GAIN

SELECTION

IxN, VN

IxP, VyP

VIN

NOTES

1. x = A, B, C, N

y = A, B, C.

Figure 25. PGA in Current and Voltage Channels

VAP, VBP

OR VCP

VCM

+500mV

VCM

DIFFERENTIAL INPUT

V1 + V2 = 500mV MAX PEAK

COMMON MODE

VCM = ±25mV MAX

–500mV

Figure 26. Maximum Input Level, Voltage Channels, Gain = 1

DIGITAL

LOW-PASS

FILTER

–

CLKIN/16

INTEGRATOR

VREF

1-BIT DAC

LATCHED

COMPARATOR

ANALOG

LOW-PASS FILTER

.....10100101.....

–

Figure 27. First-Order

Σ-Δ ADC

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