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ADE7878 数据表(PDF) 85 Page - Analog Devices |
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ADE7878 数据表(HTML) 85 Page - Analog Devices |
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85 / 92 page ![]() ADE7878 Rev. 0| Page 85 of 92 Table 40. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616) Bit Location Bit Name Default Value Description 9:0 PHCALVAL 0000000000 If current channel compensation is necessary, these bits can vary only between 0 and 383. If voltage channel compensation is necessary, these bits can vary only between 512 and 575. If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves like PHCALVAL set between 256 and 383. If the PHCALVAL bits are set with numbers between 512 and 1023, the compensation behaves like PHCALVAL bits set between 384 and 511. 15:10 Reserved 000000 Reserved. These bits do not manage any functionality. Table 41. PHSIGN Register (Address 0xE617) Bit Location Bit Name Default Value Description 0 AWSIGN 0 0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase A is positive. 1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase A is negative. 1 BWSIGN 0 0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase B is positive. 1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase B is negative. 2 CWSIGN 0 0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase C is positive. 1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE[7:0] register (total of fundamental) on Phase C is negative. 3 SUM1SIGN 0 0: if the sum of all phase powers in the CF1 datapath is positive. 1: if the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1 datapath are identified by Bits[2:0] (TERMSEL1) of the COMPMODE[15:0] register and by Bits[2:0] (CF1SEL) of the CFMODE[15:0] register. 4 AVARSIGN 0 0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase A is positive. 1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase A is negative. 5 BVARSIGN 0 0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase B is positive. 1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase B is negative. 6 CVARSIGN 0 0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase C is positive. 1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total of fundamental) on Phase C is negative. 7 SUM2SIGN 0 0: if the sum of all phase powers in the CF2 datapath is positive. 1: if the sum of all phase powers in the CF2 datapath is negative. Phase powers in the CF2 datapath are identified by Bits[5:3] (TERMSEL2) of the COMPMODE[15:0] register and by Bits[5:3] (CF2SEL) of the CFMODE[15:0] register. 8 SUM3SIGN 0 0: if the sum of all phase powers in the CF3 datapath is positive. 1: if the sum of all phase powers in the CF3 datapath is negative. Phase powers in the CF3 datapath are identified by Bits[8:6] (TERMSEL3) of the COMPMODE[15:0] register and by Bits[8:6] (CF3SEL) of the CFMODE[15:0] register. 15:9 Reserved 000 0000 Reserved. These bits are always 0. |
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