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ADE7878 数据表(PDF) 50 Page - Analog Devices |
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ADE7878 数据表(HTML) 50 Page - Analog Devices |
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50 / 92 page  ADE7878 Rev. 0 | Page 50 of 92 energy registers, xVARHR (for REHF interrupt) or xFVARHR (for FREHF interrupt), becomes half full. The status bit is cleared and the IRQ0 pin is set to high by writing to the STATUS0 register with the corresponding bit set to 1. Setting Bit 6 (RSTREAD) of LCYMODE[7:0] register enables a read-with-reset for all var-hour accumulation registers, that is, the registers are reset to 0 after a read operation. AVGAIN HPFDIS [23:0] HPF AIGAIN HPFDIS [23:0] DIGITAL INTEGRATOR REVRPA BIT IN STATUS0[31:0] HPF VA IA AVARGAIN AVAROS APHCAL ACCUMULATOR VARTHR[47:0] AVARHR[31:0] 32 BIT REGISTER TOTAL REACTIVE POWER ALGORITHM DIGITAL SIGNAL PROCESSOR Figure 65. Total Reactive Energy Accumulation |
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