ADE7878 datasheet(19/92 Pages) AD

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ADE7878

Rev. 0 | Page 19 of 92

POWER MANAGEMENT

The ADE7878 has four modes of operation, determined by the

state of the PM0 and PM1 pins (see Table 8). These pins provide

complete control of the ADE7878 operation and can easily be

connected to an external microprocessor I/O. The PM0 and

PM1 pins have internal pull-up resistors. Table 10 and Table 11

list actions that are recommended before and after setting a new

power mode.

Table 8. ADE7878 Power Supply Modes

Power Supply Modes

PM1

PM0

PSM0, Normal Power Mode

PSM1, Reduced Power Mode

PSM2, Low Power Mode

PSM3, Sleep Mode

PSM0—NORMAL POWER MODE

In PSM0 mode, the ADE7878 is fully functional. The PM0 pin

is set to high and the PM1 pin is set to low for the ADE7878 to

enter this mode. If the ADE7878 is in one of PSM1, PSM2, or

PSM3 modes and is switched into PSM0 mode, then all control

registers take the default values with the exception of the threshold

CONFIG2[7:0] register, both of which maintain their values.

The ADE7878 signals the end of the transition period by triggering

the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in

the STATUS1[31:0] register to 1. This bit is 0 during the transition

period and becomes 1 when the transition is finished. The status

bit is cleared and the IRQ1 pin is set back to high by writing

STATUS1[31:0] register with the corresponding bit set to 1.

Bit 15 (RSTDONE) in the interrupt mask register does not have

any functionality attached even if the IRQ1 pin goes low when

Bit 15 (RSTDONE) in the STATUS1[31:0] register is set to 1.

This makes the RSTDONE interrupt unmaskable.

PSM1—REDUCED POWER MODE

In this mode, the ADE7878 measures the mean absolute values

(mav) of the 3-phase currents and stores the results in the

AIMAV[19:0], BIMAV[19:0], and CIMAV[19:0] 20-bit

registers. This mode is useful in missing neutral cases in which

the voltage supply of the ADE7878 is provided by an external

battery. The serial ports, I2C or SPI, are enabled in this mode

and the active port can be used to read the AIMAV, BIMAV, and

CIMAV registers. It is not recommended to read any of the other

registers because their values are not guaranteed in this mode.

Similarly, a write operation is not taken into account by the

ADE7878 in this mode. In summary, in this mode, it is not

recommended to access any register other than AIMAV,

BIMAV, and CIMAV. The circuit that measures these estimates

of rms values is also active during PSM0; therefore, its calibration

can be completed in either PSM0 mode or in PSM1 mode. Note

that the ADE7878 does not provide any register to store or

process the corrections resulting from the calibration process.

The external microprocessor should store the gain values in

connection with these measurements and use them during

PSM1 (see the Current Mean Absolute Value Calculation

section for more details on the xIMAV registers).

The 20-bit mean absolute value measurements done in PSM1,

although available also in PSM0, are different from the rms

measurements of phase currents and voltages executed only in

PSM0 and stored in xIRMS and xVRMS 24-bit registers. See the

Current Mean Absolute Value Calculation section for details.

If the ADE7878 is set in PSM1 mode while still in PSM0, the

ADE7878 immediately begins the mean absolute value calcula-

tions without any delay. The xIMAV registers can be accessed at

any time; however, if the ADE7878 is set in PSM1 mode while

still in PSM2 or PSM3 modes, the ADE7878 signals the start of

the mean absolute value computations by triggering the IRQ1

pin low. The xIMAV registers can be accessed only after this

moment.

PSM2—LOW POWER MODE

In this mode, the ADE7878 compares all phase currents against

a threshold for a period of 0.02 × (LPLINE + 1) seconds,

independent of the line frequency. LPLINE are Bits[7:3] of the

LPOILVL[7:0] register (see Table 9).

Table 9. LPOILVL Register

Bit

Mnemonic

Default

Description

[2:0]

LPOIL

111

Threshold is put at a value

corresponding to full scale

multiplied by LPOIL/8.

[7:3]

LPLINE

00000

The measurement period is

(LPLINE + 1)/50 sec.

The threshold is derived from Bits[2:0] (LPOIL) of the

LPOILVL[7:0] register as LPOIL/8 of full scale. Every time

one phase current becomes greater than the threshold, a

counter is incremented. If every phase counter remains below

LPLINE + 1 at the end of the measurement period, then the

IRQ0 pin is triggered low. If a single phase counter becomes

greater or equal to LPLINE + 1 at the end of the measurement

period, the IRQ1 pin is triggered low.

illustrates how

the ADE7878 behaves in PSM2 mode when LPLINE = 2 and

LPOIL = 3. The test period is three 50 Hz cycles (60 ms), and

the Phase A current rises above the LPOIL threshold three times.

At the end of the test period, the

Figure 22

IRQ1 pin is triggered low.

The I2C or SPI port is not functional during this mode. The

PSM2 mode reduces the power consumption required to mon-

itor the currents when there is no voltage input and the voltage

supply of the ADE7878 is provided by an external battery. If the

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