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ADE7878 数据表(PDF) 82 Page - Analog Devices

部件名 ADE7878
功能描述  Polyphase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  92 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7878 数据表(HTML) 82 Page - Analog Devices

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ADE7878
Rev. 0| Page 82 of 92
Bit Location
Bit Name
Default Value
Description
12
VSPHASE[0]
0
When this bit is set to 1, the Phase A voltage generated Bit 16 (SAG) in the
STATUS1[31:0] register.
13
VSPHASE[1]
0
When this bit is set to 1, the Phase B voltage generated Bit 16 (SAG) in the
STATUS1[31:0] register.
14
VSPHASE[2]
0
When this bit is set to 1, the Phase C voltage generated Bit16 (SAG) in the STATUS1[31:0]
register.
15
Reserved
0
Reserved. This bit is always 0.
Table 36. PHNOLOAD Register (Address 0xE608)
Bit
Location
Bit Name
Default Value
Description
0
NLPHASE[0]
0
0: Phase A is out of no load condition based on total active/reactive powers.
1: Phase A is in no load condition based on total active/reactive powers. This bit is set
together with Bit 0 (NLOAD) in the STATUS1[31:0] register.
1
NLPHASE[1]
0
0: Phase B is out of no load condition based on total active/reactive powers.
1: Phase B is in no load condition based on total active/reactive powers. This bit is set
together with Bit 0 (NLOAD) in the STATUS1[31:0] register.
2
NLPHASE[2]
0
0: Phase C is out of no load condition based on total active/reactive powers.
1: Phase C is in no load condition based on total active/reactive powers. This bit is set
together with Bit 0 (NLOAD) in the STATUS1[31:0] register.
3
FNLPHASE[0]
0
0: Phase A is out of no load condition based on fundamental active/reactive powers.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1[31:0].
4
FNLPHASE[1]
0
0: Phase B is out of no load condition based on fundamental active/reactive powers.
1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1[31:0].
5
FNLPHASE[2]
0
0: Phase C is out of no load condition based on fundamental active/reactive powers.
1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1[31:0].
6
VANLPHASE[0]
0
0: Phase A is out of no load condition based on apparent power.
1: Phase A is in no load condition based on apparent power. This bit is set together with Bit 2
(VANLOAD) in the STATUS1[31:0] register.
7
VANLPHASE[1]
0
0: Phase B is out of no load condition based on apparent power.
1: Phase B is in no load condition based on apparent power. This bit is set together with Bit 2
(VANLOAD) in the STATUS1[31:0] register.
8
VANLPHASE[2]
0
0: Phase C is out of no load condition based on apparent power.
1: Phase C is in no load condition based on apparent power. This bit is set together with Bit 2
(VANLOAD) in the STATUS1[31:0] register.
15:9
Reserved
000 0000
Reserved. These bits are always 0.
Table 37. COMPMODE Register (Address 0xE60E)
Bit
Location
Bit Name
Default
Value
Description
0
TERMSEL1[0]
1
Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1 output.
Phase A is included in the CF1 outputs calculations.
1
TERMSEL1[1]
1
Phase B is included in the CF1 outputs calculations.
2
TERMSEL1[2]
1
Phase C is included in the CF1 outputs calculations.
3
TERMSEL2[0]
1
Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2 output.
Phase A is included in the CF2 outputs calculations.
4
TERMSEL2[1]
1
Phase B is included in the CF2 outputs calculations.
5
TERMSEL2[2]
1
Phase C is included in the CF2 outputs calculations.
6
TERMSEL3[0]
1
Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3 output.
Phase A is included in the CF3 outputs calculations.



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