ADE7878 datasheet(87/92 Pages) AD

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ADE7878

Rev. 0| Page 87 of 92

Table 43. MMODE Register (Address 0xE700)

Bit

Location

Bit Name

Default Value

Description

1:0

PERSEL[1:0]

00: Phase A selected as the source of the voltage line period measurement.

01: Phase B selected as the source of the voltage line period measurement.

10: Phase C selected as the source of the voltage line period measurement.

11: reserved. When set, the ADE7878 behaves like PERSEL[1:0] = 00.

PEAKSEL[0]

PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three

phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak

measurement period indicated in the PEAKCYC[7:0] register decreases accordingly because

zero crossings are detected on more than one phase.

When this bit is set to 1, Phase A is selected for the voltage and current peak registers.

PEAKSEL[1]

When this bit is set to 1, Phase B is selected for the voltage and current peak registers.

PEAKSEL[2]

When this bit is set to 1, Phase C is selected for the voltage and current peak registers.

7:5

Reserved

000

Reserved. These bits do not manage any functionality.

Table 44. ACCMODE Register (Address 0xE701)

Bit

Location

Bit Name

Default Value

Description

1:0

WATTACC[1:0]

00: signed accumulation mode of the total active and fundamental powers.

01: reserved. When set, the ADE7878 behaves like WATTACC[1:0] = 00.

10: reserved. When set, the ADE7878 behaves like WATTACC[1:0] = 00.

11: absolute accumulation mode of the total active and fundamental powers.

3:2

VARACC[1:0]

00: signed accumulation of the total reactive and fundamental powers.

01: reserved. When set, the ADE7878 behaves like VARACC[1:0] = 00.

10: the total reactive and fundamental powers are accumulated, depending on the sign of

the total active and fundamental power: if the active power is positive, the reactive power is

accumulated as is, whereas if the active power is negative, the reactive power is

accumulated with reversed sign.

11: reserved. When set, theADE7878 behaves like VARACC[1:0] = 00.

5:4

CONSEL[1:0]

These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB, and

IC shifted respectively by −90°. See Table 45.

00: 3-phase four wires with three voltage sensors.

01: 3-phase three wires delta connection.

10: 3-phase four wires with two voltage sensors.

11: 3-phase four wires delta connection.

REVAPSEL

0: the total active power on each phase is used to trigger a bit in the STATUS0[31:0] register

as follows: on Phase A, triggers Bit 6 (REVAPA); on Phase B, triggers Bit 7 (REVAPB); and on

Phase C, triggers Bit 8 (REVAPC).

1: the fundamental active power on each phase is used to trigger a bit in the STATUS0[31:0]

on Phase C triggers Bit 8 (REVAPC).

REVRPSEL

0: the total active power on each phase is used to trigger a bit in the STATUS0[31:0] register

as follows: on Phase A, triggers Bit 10 (REVRPA); on Phase B, triggers Bit 11 (REVRPB); and on

Phase C, triggers Bit 12 (REVRPC).

1: the fundamental active power on each phase is used to trigger a bit in the STATUS0[31:0]

and on Phase C, triggers Bit 12 (REVRPC).

ADE7878 数据表(PDF) 87 Page - Analog Devices

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