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ADE7878 数据表(PDF) 76 Page - Analog Devices

部件名 ADE7878
功能描述  Polyphase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  92 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7878 数据表(HTML) 76 Page - Analog Devices

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ADE7878
Rev. 0 | Page 76 of 92
Address
Name
R/W1
Bit
Length
Bit Length During
Communication2
Type3
Default
Value4
Description
0xE600
PHSTATUS
R
16
16
U
N/A
Phase peak register. See Table 35.
0xE601
ANGLE0
R
16
16
U
N/A
Time Delay 0. See the Time Interval
Between Phases section for details.
0xE602
ANGLE1
R
16
16
U
N/A
Time Delay 1. See the Time Interval
Between Phases section for details.
0xE603
ANGLE2
R
16
16
U
N/A
Time Delay 2. See the Time Interval
Between Phases section for details.
0xE604 to
0xE606
Reserved
These addresses should not be
written for proper operation.
0xE607
PERIOD
R
16
16
U
N/A
Network line period.
0xE608
PHNOLOAD
R
16
16
U
NA
Phase no load register. See Table 36.
0xE609 to
0xE60B
Reserved
These addresses should not be
written for proper operation.
0xE60C
LINECYC
R/W
16
16
U
0xFFFF
Line cycle accumulation mode count.
0xE60D
ZXTOUT
R/W
16
16
U
0xFFFF
Zero-crossing timeout count.
0xE60E
COMPMODE
R/W
16
16
U
0x01FF
Computation-mode register. See
Table 37.
0xE60F
GAIN
R/W
16
16
U
0x0000
PGA gains at ADC inputs. See
Table 38.
0xE610
CFMODE
R/W
16
16
U
0x0E88
CFx configuration register. See Table 39.
0xE611
CF1DEN
R/W
16
16
U
0x0000
CF1 denominator.
0xE612
CF2DEN
R/W
16
16
U
0x0000
CF2 denominator.
0xE613
CF3DEN
R/W
16
16
U
0x0000
CF3 denominator.
0xE614
APHCAL
R/W
10
16 ZP
U
0x0000
Phase calibration of Phase A. See
Table 40.
0xE615
BPHCAL
R/W
10
16 ZP
U
0x0000
Phase calibration of Phase B. See
Table 40.
0xE616
CPHCAL
R/W
10
16 ZP
U
0x0000
Phase calibration Phase of C. See
Table 40.
0xE617
PHSIGN
R
16
16
U
NA
Power sign register. See Table 41.
0xE618
CONFIG
R/W
16
16
U
0x0000
ADE7878 configuration register. See
Table 42.
0xE700
MMODE
R/W
8
8
U
0x16
Measurement mode register.
See Table 43.
0xE701
ACCMODE
R/W
8
8
U
0x00
Accumulation mode register.
See Table 44.
0xE702
LCYCMODE
R/W
8
8
U
0x78
Line accumulation mode behavior.
See Table 46.
0xE703
PEAKCYC
R/W
8
8
U
0x00
Peak detection half-line cycles.
0xE704
SAGCYC
R/W
8
8
U
0x00
Sag detection half-line cycles.
0xE705
CFCYC
R/W
8
8
U
0x01
Number of CF pulses between two
consecutive energy latches. See the
Synchronizing Energy Registers with
CFx Outputs section.
0xE706
HSDC_CFG
R/W
8
8
U
0x00
HSDC configuration register. See
Table 47.
0xE707
VERSION
R/W
8
8
U
Version of die.
0xEBFF
Reserved
8
8
This address can be used in
manipulating the SS pin when SPI is
chosen as the active port. See the
Serial Interfaces section for details.



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