ADE7878 datasheet(43/92 Pages) AD

43 / 92 page

ADE7878

Rev. 0 | Page 43 of 92

Fundamental Active Power Calculation

The ADE7878 computes the fundamental active power using

a proprietary algorithm that requires some initializations

function of the frequency of the network and its nominal

voltage measured in the voltage channel. Bit 14 (SELFREQ) in

the COMPMODE[15:0] register must be set according to the

frequency of the network in which the ADE7878 is connected.

If the network frequency is 50 Hz, then clear this bit to 0 (the

default value). If the network frequency is 60 Hz, then set this

bit to 1. Also, the VLEVEL[23:0] 24-bit signed register should

be initialized with a positive value based on the following

expression:

520

491

VLEVEL

(21)

where:

UFS is the rms value of the phase voltages when the ADC inputs

are at full scale.

Un is the rms nominal value of the phase voltage.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. Similar

to the registers presented in Figure 32, the VLEVEL[23:0] 24-bit

signed register is accessed as a 32-bit register with the four most

significant bits padded with 0s and sign extended to 28 bits.

Table 13 presents the settling time for the fundamental active

power measurement.

Table 13.Settling Time for Fundamental Active Power

Input Signals

63% Full Scale

100% Full Scale

375 ms

875 ms

Active Power Gain Calibration

Note that the average active power result from the LPF2 output

in each phase can be scaled by ±100% by writing to the phase’s

watt gain 24-bit register, (AWGAIN[23:0], BWGAIN[23:0],

CWGAIN[23:0], AFWGAIN[23:0], BFWGAIN[23:0], or

CFWGAIN[23:0]). The xWGAIN registers are placed in each

phase of the total active power datapath, and the xFWGAIN

registers are placed in each phase of the fundamental active

power datapath. The watt gain registers are twos complement

signed registers and have a resolution of 2−23/LSB. Equation 22

describes mathematically the function of the watt gain registers.

⎟

⎠

⎞

⎜

⎝

⎛ +

gister

Gain

Watt

Output

LPF

Data

Power

Average

(22)

The output is scaled by −50% by writing 0xC00000 to the watt

gain registers, and it is increased by +50% by writing 0x400000

to them. These registers can be used to calibrate the active

power (or energy) calculation in the ADE7878 for each phase.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. Similar

to registers presented in Figure 32, the AWGAIN, BWGAIN,

CWGAIN, AFWGAIN, BFWGAIN, and CFWGAIN 24-bit

signed registers are accessed as 32-bit registers with the four

MSBs padded with 0s and sign extended to 28 bits.

Active Power Offset Calibration

The ADE7878 also incorporates a watt offset 24-bit register

on each phase and on each active power. The AWATTOS[23:0],

BWATTOS[23:0], and CWATTOS[23:0] registers compensate

the offsets in the total active power calculations, and the

AFWATTOS[23:0], BFWATTOS[23:0], and CFWATTOS[23:0]

registers compensate offsets in the fundamental active power

calculations. These are signed twos complement 24-bit registers

that are used to remove offsets in the active power calculations.

An offset can exist in the power calculation due to crosstalk

between channels on the PCB or in the chip itself. The offset

calibration allows the contents of the active power register to be

maintained at 0 when no power is being consumed. One LSB in

the active power offset register is equivalent to 1 LSB in the

active power multiplier output. With full-scale current and

voltage inputs, the LPF2 output is PMAX = 33,516,139. At

−80 dB down from the full scale (active power scaled down 104

times), one LSB of the active power offset register represents

0.0298% of PMAX.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. Similar

to registers presented in Figure 32, the AWATTOS, BWATTOS,

and CWATTOS, AFWATTOS, BFWATTOS, CFWATTOS

24-bit signed registers are accessed as 32-bit registers with the

four MSBs padded with 0s and sign extended to 28 bits.

Sign of Active Power Calculation

Note that the average active power is a signed calculation. If the

phase difference between the current and voltage waveform is

more than 90°, the average power becomes negative. Negative

power indicates that energy is being injected back on the grid.

The ADE7878 has sign detection circuitry for total active power

calculations. It can monitor the total active powers or the funda-

mental active powers. As described in the Active Energy

Calculation section, the active energy accumulation is performed

in two stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is, after the

energy accumulated into the internal accumulator reaches the

WTHR[47:0] threshold, a dedicated interrupt is triggered. The

sign of each phase active power can be read in the PHSIGN[15:0]

Bit 6 (REVAPSEL) in the ACCMODE[7:0] register sets the type

of active power being monitored. When REVAPSEL is 0, the

default value, the total active power is monitored. When

REVAPSEL is 1, the fundamental active power is monitored.

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