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ADE7878 数据表(PDF) 74 Page - Analog Devices

部件名 ADE7878
功能描述  Polyphase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  92 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7878 数据表(HTML) 74 Page - Analog Devices

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ADE7878
Rev. 0 | Page 74 of 92
Table 25. Internal DSP Memory RAM Registers
Address
Name
R/W1
Bit
Length
Bit Length During
Communication
Type2
Default
Value
Description
0xE203
Reserved
R/W
16
16
U
0x0000
This memory location should not be written for
proper operation.
0xE228
Run
R/W
16
16
U
0x0000
The run register starts and stops the DSP. See the
Digital Signal Processor section for more details.
1 R is read and W is write.
2 U is an unsigned register and S is a signed register in twos complement format.
Table 26. Billable Registers
Address
Register
Name
R/W1
Bit
Length
Bit Length
During
Communication
Type 2
Default
Value
Description
0xE400
AWATTHR
R
32
32
S
0x00000000
Phase A total active energy accumulation.
0xE401
BWATTHR
R
32
32
S
0x00000000
Phase B total active energy accumulation.
0xE402
CWATTHR
R
32
32
S
0x00000000
Phase C total active energy accumulation.
0xE403
AFWATTHR
R
32
32
S
0x00000000
Phase A fundamental active energy
accumulation.
0xE404
BFWATTHR
R
32
32
S
0x00000000
Phase B fundamental active energy
accumulation.
0xE405
CFWATTHR
R
32
32
S
0x00000000
Phase C fundamental active energy
accumulation.
0xE406
AVARHR
R
32
32
S
0x00000000
Phase A total reactive energy accumulation.
0xE407
BVARHR
R
32
32
S
0x00000000
Phase B total reactive energy accumulation.
0xE408
CVARHR
R
32
32
S
0x00000000
Phase C total reactive energy accumulation.
0xE409
AFVARHR
R
32
32
S
0x00000000
Phase A fundamental reactive energy
accumulation.
0xE40A
BFVARHR
R
32
32
S
0x00000000
Phase B fundamental reactive energy
accumulation.
0xE40B
CFVARHR
R
32
32
S
0x00000000
Phase C fundamental reactive energy
accumulation.
0xE40C
AVAHR
R
32
32
S
0x00000000
Phase A apparent energy accumulation.
0xE40D
BVAHR
R
32
32
S
0x00000000
Phase B apparent energy accumulation.
0xE40E
CVAHR
R
32
32
S
0x00000000
Phase C apparent energy accumulation.
1 R is read and W is write.
2 U is an unsigned register and S is a signed register in twos complement format.
Table 27. Configuration and Power Quality Registers
Address
Name
R/W1
Bit
Length
Bit Length During
Communication2
Type3
Default
Value4
Description
0xE500
IPEAK
R
32
32
U
N/A
Current peak register. See Figure 47
and Table 29 for details about its
composition.
0xE501
VPEAK
R
32
32
U
N/A
Voltage peak register. See Figure 47
and Table 30 for details about its
composition.
0xE502
STATUS0
R
32
32
U
N/A
Interrupt Status Register 0. See Table 31.
0xE503
STATUS1
R
32
32
U
N/A
Interrupt Status Register 1. See Table 32.
0xE504
AIMAV
R
20
32 ZP
U
N/A
Phase A current mean absolute value
computed during PSM0 and PSM1
modes.



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