ADE7878 datasheet(65/92 Pages) AD

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ADE7878

Rev. 0 | Page 65 of 92

SPI-Compatible Interface

The SPI of the ADE7878 is always a slave of the communication

and consists of four pins: SCLK, MOSI, MISO, and SS. The

serial clock for a data transfer is applied at the SCLK logic input.

This logic input has a Schmitt trigger input structure that allows

slow rising (and falling) clock edges to be used. All data transfer

operations are synchronized to the serial clock. Data is shifted

into the ADE7878 at the MOSI logic input on the falling edge of

SCLK, and the ADE7878 samples it on the rising edge of SCLK.

Data is shifted out of the ADE7878 at the MISO logic output on

a falling edge of SCLK and can be sampled by the master device

on the rising edge of SCLK. The most significant bit of the word

is shifted in and out first. The maximum serial clock frequency

supported by this interface is 2.5 MHz. MISO stays in high

impedance when no data is transmitted from the ADE7878.

presents details of the connection between the ADE7878

SPI and a master device containing an SPI interface.

Figure 82

The SS logic input is the chip select input. This input is used

when multiple devices share the serial bus. The SS input should

be driven low for the entire data transfer operation. Bringing SS

high during a data transfer operation aborts the transfer and

places the serial bus in a high impedance state. A new transfer

can then be initiated by bringing the SS logic input back low.

However, because aborting a data transfer before completion

leaves the accessed register in a state that cannot be guaranteed,

every time a register is written, its value should be verified by

reading it back. The protocol is similar to the protocol used in

I2C interface.

MOSI

MISO

SCLK

ADE7878

MOSI

MISO

SCK

SPI DEVICE

Figure 82. Connecting ADE7878 SPI with an SPI Device

SPI Read Operation

The read operation using the SPI interface of the ADE7878

initiates when the master sets the SS pin low and begins sending

one byte representing the address of the ADE7878 on the MOSI

line. The master sets data on the MOSI line starting with the

first high-to-low transition of SCLK. The SPI of the ADE7878

samples data on the low-to-high transitions of SCLK. The most

significant seven bits of the address byte can have any value, but

as a good programming practice, they should be different from

0111000b, the seven bits used in the I2C protocol. Bit 0

(read/write) of the address byte must be 1 for a read operation.

Next, the master sends the 16-bit address of the register that is

read. After the ADE7878 receives the last bit of address of the

transmit its contents on the MISO line when the next SCLK

high-to-low transition occurs; thus, the master can sample the

data on a low-to-high SCLK transition. After the master

receives the last bit, it sets the SS and SCLK lines high and the

communication ends. The data lines, MOSI and MISO, go into

a high impedance state. See

for details of the SPI read

operation.

Figure 83

SPI Write Operation

The write operation using the SPI interface of the ADE7878

initiates when the master sets the SS pin low and begins sending

one byte representing the address of the ADE7878 on the MOSI

line. The master sets data on the MOSI line starting with the

first high-to-low transition of SCLK. The SPI of the ADE7878

samples data on the low-to-high transitions of SCLK. The most

significant seven bits of the address byte can have any value, but

as a good programming practice, they should be different from

0111000b, the seven bits used in the I2C protocol. Bit 0

(read/write) of the address byte must be 0 for a write operation.

Next, the master sends the 16-bit address of the register that is

written and the 32-, 16-, or 8-bit value of that register without

losing any SCLK cycle. After the last bit is transmitted, the

master sets the SS and SCLK lines high at the end of SCLK cycle

and the communication ends. The data lines MOSI and MISO

go into high impedance state.

See Figure 84 for details of the SPI write operation.

HSDC Interface

The high speed data capture (HSDC) interface is disabled after

default. It can be used only if the ADE7878 is configured with

an I2C interface. The SPI interface cannot be used in conjunc-

tion with HSDC. Bit 6 (HSDCEN) in the CONFIG[15:0]

to 0, the default value, the HSDC interface is disabled. Setting

Bit HSDCEN to 1 when SPI is in use does not have any effect.

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