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ADE7878 数据表(PDF) 81 Page - Analog Devices

部件名 ADE7878
功能描述  Polyphase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  92 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7878 数据表(HTML) 81 Page - Analog Devices

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ADE7878
Rev. 0| Page 81 of 92
Bit
Location
Bit Name
Default Value
Description
7
ZXTOIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B current is
missing.
8
ZXTOIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C current is
missing.
9
ZXVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the Phase A
voltage.
10
ZXVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the Phase B
voltage.
11
ZXVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the Phase C
voltage.
12
ZXIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the Phase A
current.
13
ZXIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the Phase B
current.
14
ZXIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the Phase C
current.
15
RSTDONE
0
Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
16
SAG
0
When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the phases
indicated by Bits[14:12] (VSPHASE) in the PHSTATUS[15:0] register (see Table 35).
17
OI
0
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of the
phases indicated by Bits[5:3] (OIPHASE) in the PHSTATUS[15:0] register (see Table 35).
18
OV
0
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of the
phases indicated by Bits[11:9] (OVPHASE) in the PHSTATUS[15:0] register (see Table 35).
19
SEQERR
0
When this bit is set to 1, it enables an interrupt when a negative-to-positive zero crossing on
Phase A voltage is not followed by a negative-to-positive zero crossing on Phase B voltage, but by
a negative-to-positive zero crossing on the Phase C voltage.
20
MISMTCH
0
ISUMLVL
INWV
ISUM
>
−
When this bit is set to 1, it enables an interrupt when
is greater
than the value indicated in the ISUMLVL[23:0] register.
22:21
Reserved
00
Reserved. These bits do not manage any functionality.
23
PKI
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in
the current channel has ended.
24
PKV
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in
the voltage channel has ended.
31:25
Reserved
000 0000
Reserved. These bits do not manage any functionality.
Table 35. PHSTATUS Register (Address 0xE600)
Bit Location
Bit Name
Default Value
Description
2:0
Reserved
000
Reserved. These bits are always 0.
3
OIPHASE[0]
0
When this bit is set to 1, the Phase A current generated Bit 17 (OI) in the STATUS1[31:0]
register.
4
OIPHASE[1]
0
When this bit is set to 1, the Phase B current generated Bit 17 (OI) in the STATUS1[31:0]
register.
5
OIPHASE[2]
0
When this bit is set to 1, the Phase C current generated Bit 17 (OI) in the STATUS1[31:0]
register.
8:6
Reserved
000
Reserved. These bits are always 0.
9
OVPHASE[0]
0
When this bit is set to 1, the Phase A voltage generated Bit 18 (OV) in the STATUS1[31:0]
register.
10
OVPHASE[1]
0
When this bit is set to 1, the Phase B voltage generated Bit 18 (OV) in the STATUS1[31:0]
register.
11
OVPHASE[2]
0
When this bit is set to 1, the Phase C voltage generated Bit 18 (OV) in the STATUS1[31:0]
register.



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