ADE7878 datasheet(79/92 Pages) AD

79 / 92 page

ADE7878

Rev. 0| Page 79 of 92

Bit

Location

Bit Name

Default Value

Description

ZXTOVC

When this bit is set to 1, it indicates that a zero crossing on Phase C voltage is missing.

ZXTOIA

When this bit is set to 1, it indicates that a zero crossing on Phase A current is missing.

ZXTOIB

When this bit is set to 1, it indicates that a zero crossing on Phase B current is missing.

ZXTOIC

When this bit is set to 1, it indicates that a zero crossing on Phase C current is missing.

ZXVA

When this bit is set to 1, it indicates that a zero crossing has been detected on Phase A voltage.

ZXVB

When this bit is set to 1, it indicates that a zero crossing has been detected on Phase B voltage.

ZXVC

When this bit is set to 1, it indicates that a zero crossing has been detected on Phase C voltage.

ZXIA

When this bit is set to 1, it indicates that a zero crossing has been detected on Phase A current.

ZXIB

When this bit is set to 1, it indicates that a zero crossing has been detected on Phase B current.

ZXIC

When this bit is set to 1, it indicates that a zero crossing has been detected on Phase C current.

RSTDONE

In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG[15:0] register, or

a transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set to 1 at the

end of the transition process and after all registers changed value to the default. TheIRQ1

pin goes low to signal this moment because this interrupt cannot be disabled.

SAG

When this bit is set to 1, it indicates a SAG event has occurred on one of the phases indicated

by Bits[14:12] (VSPHASE) in the PHSTATUS[15:0] register (see Table 35).

When this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases

indicated by Bits[5:3] (OIPHASE) in the PHSTATUS[15:0] register (see Table 35).

When this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases

indicated by Bits[11:9] (OVPHASE) in the PHSTATUS[15:0] register (see Table 35).

SEQERR

When this bit is set to 1, it indicates a negative-to-positive zero crossing on the Phase A

voltage was not followed by a negative-to-positive zero crossing on the Phase B voltage but

by a negative-to-positive zero crossing on the Phase C voltage.

MISMTCH

When this bit is set to 1, it indicates

ISUMLVL

INWV

ISUM

−

, where ISUMLVL is

indicated in the ISUMLVL[23:0] register.

(Reserved)

Reserved. This bit is always set to 1.

(Reserved)

Reserved. This bit is always set to 0.

PKI

When this bit is set to 1, it indicates that the period used to detect the peak value in the

current channel has ended. The IPEAK[31:0] register contains the peak value and the phase

where the peak has been detected (see Table 29).

PKV

When this bit is set to 1, it indicates that the period used to detect the peak value in the

voltage channel has ended. The VPEAK[31:0] register contains the peak value and the phase

where the peak has been detected (see Table 30).

31:25

Reserved

000 0000

Reserved. These bits are always 0.

Table 33. MASK0 Register (Address 0xE50A)

Bit

Location

Bit Name

Default Value

Description

AEHF

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total active energy

registers (AWATTHR, BWATTHR, CWATTHR) changes.

FAEHF

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental active

energy registers (AFWATTHR, BFWATTHR, or CFWATTHR) changes.

REHF

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total reactive

energy registers (AVARHR, BVARHR, CVARHR) changes.

FREHF

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental

reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes.

VAEHF

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent energy

registers (AVAHR, BVAHR, CVAHR) changes.

LENERGY

When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end of

an integration over an integer number of half-line cycles set in the LINECYC[15:0] register.

ADE7878 数据表(PDF) 79 Page - Analog Devices

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