ADE7878 datasheet(48/92 Pages) AD

48 / 92 page

ADE7878

Rev. 0 | Page 48 of 92

Table 16 presents the settling time for the fundamental reactive

power measurement, which is the time it takes the power to

reflect the value at the input of theADE7878.

Table 16. Settling Time for Fundamental Reactive Power

Input Signals

63% Full Scale

100% Full Scale

375 ms

875 ms

Reactive Power Gain Calibration

The average reactive power from the LPF output in each phase

can be scaled by ±100% by writing to the phase’s VAR gain 24-bit

AFVARGAIN[23:0], BFVARGAIN[23:0], or CFVARGAIN[23:0]).

The xVARGAIN registers are placed in each phase of the total

reactive power datapath. The xFVARGAIN registers are placed in

each phase of the fundamental reactive power datapath. The

xVARGAIN registers are twos complement signed registers and

have a resolution of 2−23/LSB. The function of the xVARGAIN

registers is expressed by

⎟

⎠

⎞

⎜

⎝

⎛ +

gister

xVARGAIN

Output

LPF

Power

Reactive

Average

(35)

The output is scaled by –50% by writing 0xC00000 to the

xVARGAIN registers and increased by +50% by writing

0x400000 to them. These registers can be used to calibrate the

reactive power (or energy) gain in the ADE7878 for each phase.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. Similar

to registers presented in Figure 32, the AVARGAIN,

BVARGAIN, CVARGAIN, AFVARGAIN, BFVARGAIN, and

CFVARGAIN 24-bit signed registers are accessed as 32-bit

registers with the four MSBs padded with 0s and sign extended

to 28 bits.

Reactive Power Offset Calibration

The ADE7878 provides a reactive power offset register on

each phase and on each reactive power. The AVAROS[23:0],

BVAROS[23:0], and CVAROS[23:0] registers compensate the

offsets in the total reactive power calculations, whereas the

AFVAROS[23:0], BFVAROS[23:0], and CFVAROS[23:0]

registers compensate offsets in the fundamental reactive power

calculations. These are signed twos complement 24-bit registers

that are used to remove offsets in the reactive power

calculations. An offset can exist in the power calculation due to

crosstalk between channels on the PCB or in the chip itself. The

offset calibration allows the contents of the reactive power

consumed. The offset resolution of the registers is the same as

for the active power offset registers (see the Active Power Offset

Calibration section).

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. Similar

to registers presented in Figure 32, the AVAROS, BVAROS, and

CVAROS 24-bit signed registers are accessed as 32-bit registers

with the four MSBs padded with 0s and sign extended to 28 bits.

Sign of Reactive Power Calculation

Note that the reactive power is a signed calculation. Table 17

summarizes the relationship between the phase difference between

the voltage and the current and the sign of the resulting reactive

power calculation.

The ADE7878 has a sign detection circuitry for reactive power

calculations. It can monitor the total reactive powers or the

fundamental reactive powers. As described in the Reactive

Energy Calculation section, the reactive energy accumulation is

executed in two stages. Every time a sign change is detected in

the energy accumulation at the end of the first stage, that is,

after the energy accumulated into the 48-bit accumulator

reaches the VARTHR[47:0] register threshold, a dedicated

interrupt is triggered. The sign of each phase reactive power can

be read in the PHSIGN[15:0] register. Bit 7 (REVRPSEL) in the

ACCMODE[7:0] register sets the type of reactive power being

monitored. When REVRPSEL is 0, the default value, the total

reactive power is monitored. When REVRPSEL is 1, then the

fundamental reactive power is monitored.

Bits[12:10] (REVRPC, REVRPB, and REVRPA, respectively)

in the STATUS0[31:0] register are set when a sign change

occurs in the power selected by Bit 7 (REVRPSEL) in the

ACCMODE[7:0] register.

Bits[6:4] (CVARSIGN, BVARSIGN, and AVARSIGN, respectively)

in the PHSIGN[15:0] register are set simultaneously with the

REVRPC, REVRPB, and REVRPA bits. They indicate the sign of

the reactive power. When they are 0, the reactive power is

positive. When they are 1, the reactive power is negative.

Bit REVRPx in the STATUS0[31:0] register and Bit xVARSIGN

in the PHSIGN[15:0] register refer to the reactive power of

Phase x, the power type being selected by Bit REVRPSEL in

ACCMODE[7:0] register.

Setting Bits[12:10] in the MASK0[31:0] register enables the

REVRPC, REVRPB, and REVRPA interrupts, respectively. If

enabled, the IRQ0 pin is set low and the status bit is set to 1

whenever a change of sign occurs. To find the phase that

triggered the interrupt, the PHSIGN[15:0] register is read

immediately after reading the STATUS0[31:0] register. Next, the

status bit is cleared and the IRQ0 pin is set to high by writing to

the STATUS0 register with the corresponding bit set to 1.

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