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ADE7878 数据表(PDF) 84 Page - Analog Devices

部件名 ADE7878
功能描述  Polyphase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  92 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7878 数据表(HTML) 84 Page - Analog Devices

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ADE7878
Rev. 0| Page 84 of 92
Table 39. CFMODE Register (Address 0xE610)
Bit
Location
Bit Name
Default Value
Description
2:0
CF1SEL[2:0]
000
000: the CF1 frequency is proportional to the sum of total active powers on each phase
identified by Bits[2:0] (TERMSEL1) in the COMPMODE[15:0] register.
001: the CF1 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[2:0] (TERMSEL1) in the COMPMODE[15:0] register.
010: the CF1 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[2:0] (TERMSEL1) in the COMPMODE[15:0] register.
011: CF1 frequency is proportional to the sum of fundamental active powers on each phase
identified by Bits[2:0] (TERMSEL1) in the COMPMODE[15:0] register.
100: CF1 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[2:0] (TERMSEL1) in the COMPMODE[15:0] register.
101, 110, 111: reserved. When set, the ADE7878 behaves like CF1SEL[2:0] = 000.
5:3
CF2SEL[2:0]
001
000: the CF2 frequency is proportional to the sum of total active powers on each phase
identified by Bits[5:3] (TERMSEL2) in the COMPMODE[15:0] register.
001: the CF2 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[5:3] (TERMSEL2) in the COMPMODE[15:0] register.
010: the CF2 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[5:3] (TERMSEL2) in the COMPMODE[15:0] register.
011: CF2 frequency is proportional to the sum of fundamental active powers on each phase
identified by Bits[5:3] (TERMSEL2) in the COMPMODE[15:0] register.
100: CF2 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[5:3] (TERMSEL2) in the COMPMODE[15:0] register.
101,110,111: reserved. When set, theADE7878 behaves like CF2SEL[2:0] = 000.
8:6
CF3SEL[2:0]
010
000: the CF3 frequency is proportional to the sum of total active powers on each phase
identified by Bits[8:6] (TERMSEL3) in the COMPMODE[15:0] register.
001: the CF3 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[8:6] (TERMSEL3) in the COMPMODE[15:0] register.
010: the CF3 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[8:6] (TERMSEL3) in the COMPMODE[15:0] register.
011: CF3 frequency is proportional to the sum of fundamental active powers on each phase
identified by Bits[8:6] (TERMSEL3) in the COMPMODE[15:0] register.
100: CF3 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[8:6] (TERMSEL3) in the COMPMODE[15:0] register.
101,110,111: reserved. When set, the ADE7878 behaves like CF3SEL[2:0] = 000.
9
CF1DIS
1
When this bit is set to 1, the CF1 output is disabled. The respective digital to frequency
converter remains enabled even if CF1DIS = 1.
When set to 0, the CF1 output is enabled.
10
CF2DIS
1
When this bit is set to 1, the CF2 output is disabled. The respective digital to frequency
converter remains enabled even if CF2DIS = 1.
When set to 0, the CF2 output is enabled.
11
CF3DIS
1
When this bit is set to 1, the CF3 output is disabled. The respective digital to frequency
converter remains enabled even if CF3DIS = 1.
When set to 0, the CF3 output is enabled.
12
CF1LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF1 pulse is generated. See Synchronizing Energy Registers with CFx Outputs section.
13
CF2LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF2 pulse is generated. See Synchronizing Energy Registers with CFx Outputs section.
14
CF3LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF3 pulse is generated. See Synchronizing Energy Registers with CFx Outputs section.
15
Reserved
0
Reserved. This bit does not manage any functionality.



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