ADE7878 datasheet(60/92 Pages) AD

60 / 92 page

ADE7878

Rev. 0 | Page 60 of 92

No Load Detection Based on Fundamental Active and

Reactive Powers

This no load condition is triggered when the absolute values of

both phase fundamental active and reactive powers are less than or

equal to APNOLOAD[23:0] and the respective VARNOLOAD[23:0]

positive thresholds. In this case, the fundamental active and

reactive energies of that phase are not accumulated, and no CFx

pulses are generated based on these energies. APNOLOAD and

VARNOLOAD are the same no load thresholds set for the total

active and reactive powers. When APNOLOAD and VARNO-

LOAD are set to negative values, this no load detection circuit is

disabled.

Bit 1 (FNLOAD) in the STATUS1[31:0] register is set when this

no load condition in one of the three phases is triggered.

Bits[5:3] (FNLPHASE[2:0]) in the PHNOLOAD[15:0] register

indicate the state of all phases relative to a no load condition

and are set simultaneously with Bit FNLOAD in

STATUS1[31:0]. FNLPHASE[0] indicates the state of Phase A,

FNLPHASE[1] indicates the state of Phase B, and

FNLPHASE[2] indicates the state of Phase C. When Bit

FNLPHASE[x] is cleared to 0, it means the phase is out of the

no load condition. When set to 1, it means the phase is in a no

load condition.

An interrupt attached to Bit 1 (FNLOAD) in the STATUS1[31:0]

IRQ pin is set low and the status bit is

set to 1 whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD[15:0] register is read immediately after reading

STATUS1[31:0]. Then the status bit is cleared, and the

IRQ

pin is set back high by writing the STATUS1 register with the

corresponding bit set to 1.

No Load Detection Based on Apparent Power

This no load condition is triggered when the absolute value of

phase apparent power is less than or equal to the threshold

indicated in the VANOLOAD[23:0] 24-bit signed register. In

this case, the apparent energy of that phase is not accumulated

and no CFx pulses are generated based on this energy. the

VANOLOAD register represents the positive no load level of

apparent power relative to PMAX, the maximum apparent

power obtained when full-scale voltages and currents are

provided at the ADC inputs. The expression used to compute

the VANOLOAD[23:0] signed 24-bit value is

PMAX

VANOLOAD

NOLOAD

(48)

where:

PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous apparent

power computed when the ADC inputs are at full scale.

UFS, IFS are the rms values of the phase voltages and currents

when the ADC inputs are at full scale.

Un is the nominal rms value of phase voltage.

INOLOAD is the minimum rms value of phase current the meter

starts measuring.

When the VANOLOAD[23:0] register is set to negative values,

the no load detection circuit is disabled.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. Similar

to the registers presented in Figure 32, the VANOLOAD 24-bit

signed register is accessed as a 32-bit register with the four

MSBs padded with 0s and sign extended to 28 bits.

Bit 2 (VANLOAD) in the STATUS1[31:0] register is set when

this no load condition in one of the three phases is triggered.

Bits[8:6] (VANLPHASE[2:0]) in the PHNOLOAD[15:0] register

indicate the state of all phases relative to a no load condition,

and they are set simultaneously with Bit VANLOAD in the

STATUS1[31:0] register. Bit VANLPHASE[0] indicates the state

of Phase A, Bit VANLPHASE[1] indicates the state of Phase B,

and Bit VANLPHASE[2] indicates the state of Phase C. When

Bit VANLPHASE[x] is cleared to 0, it means that the phase is

out of no load condition. When set to 1, it means that the phase

is in no load condition.

An interrupt attached to Bit 2 (VANLOAD) in the STATUS1[31:0]

set to 1 whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD[15:0] register is read immediately after reading

the STATUS1[31:0] register. Next, the status bit is cleared, and

IRQ1 pin is set to high by writing to the STATUS1 register with

the corresponding bit set to 1.

CHECKSUM REGISTER

The ADE7878 has a checksum 32-bit register, CHECKSUM[31:0],

that ensures that certain very important configuration registers

maintain their desired value during Normal Power Mode

PSM0.

The registers covered by this register are MASK0[31:0],

MASK1[31:0], COMPMODE[15:0], GAIN[15:0],

CFMODE[15:0], CF1DEN[15:0], CF2DEN[15:0],

CF3DEN[15:0], CONFIG[15:0], MMODE[7:0],

ACCMODE[7:0], LCYCMODE[7:0], HSDC_CFG[7:0], and

another six 8-bit reserved internal registers that always have

default values. The ADE7878 computes the cyclic redundancy

check (CRC) based on the IEEE802.3 standard. The registers

are introduced one-by-one into a linear feedback shift register

(LFSR) based generator starting with the least significant bit

(as shown in Figure 76). The 32-bit result is written in the

CHECKSUM[31:0] register. After power-up or a hardware/

ADE7878 数据表(PDF) 60 Page - Analog Devices

ADE7878 数据表(HTML) 60 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载