ADE7878 datasheet(53/92 Pages) AD

53 / 92 page

ADE7878

Rev. 0 | Page 53 of 92

Apparent Power Gain Calibration

The average apparent power result in each phase can be scaled

by ±100% by writing to the phase’s VAGAIN 24-bit register

(AVAGAIN[23:0], BVAGAIN[23:0], or CVAG AIN[23:0]). The

VAGAIN registers are twos complement signed registers and

have a resolution of 2−23/LSB. The function of the xVAGAIN

registers is expressed mathematically as

⎟

⎠

⎞

⎜

⎝

⎛

VAGAIN

Irms

Vrms

Power

Apparent

Average

(41)

The output is scaled by –50% by writing 0xC00000 to the

xVAGAIN registers and increased by +50% by writing

0x400000 to them. These registers can be used to calibrate the

apparent power (or energy) calculation in the ADE7878 for

each phase.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. Similar

to registers presented in Figure 32, the AVAGAIN, BVAGAIN,

and CVAGAIN 24-bit registers are accessed as 32-bit registers

with the four MSBs padded with 0s and sign extended to 28 bits.

Apparent Power Offset Calibration

Each rms measurement includes an offset compensation register

to calibrate and eliminate the dc component in the rms value

(see the Root Mean Square Measurement section). The voltage

and current rms values are then multiplied together in the

apparent power signal processing. Because no additional offsets

are created in the multiplication of the rms values, there is no

specific offset compensation in the apparent power signal

processing. The offset compensation of the apparent power

measurement in each phase should be done by calibrating each

individual rms measurement.

Apparent Power Calculation Using VNOM

The ADE7878 can compute the apparent power by multiplying

the phase rms current by an rms voltage introduced externally

in the VNOM[23:0] 24-bit signed register. When one of

Bits[13:11] (VNOMCEN, VNOMBEN, or VNOMAEN) in the

COMPMODE[15:0] register is set to 1, the apparent power in

the corresponding phase (Phase x for VNOMxEN) is computed

in this way. When the VNOMxEN bits are cleared to 0, the

default value, then the arithmetic apparent power is computed.

The VNOM[23:0] register contains a number determined by U,

the desired rms voltage, and UFS, the rms value of the phase

voltage when the ADC inputs are at full scale as follows:

910

191

VNOM

(42)

where U is the nominal phase rms voltage.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words. Similar to the register presented in

Figure 33, the VNOM 24-bit signed register is accessed as a

32-bit register with the eight MSBs padded with 0s.

Apparent Energy Calculation

Apparent energy is defined as the integral of apparent power.

Apparent Energy

= ∫s(t)dt

(43)

Similar to active and reactive powers, the ADE7878 achieves the

integration of the apparent power signal in two stages (see

Figure 67). The first stage is conducted inside the DSP: every

125 μs (8 kHz frequency), the instantaneous phase apparent

power is accumulated into an internal register. When a

threshold is reached, a pulse is generated at the processor port,

and the threshold is subtracted from the internal register. The

second stage is conducted outside the DSP and consists of

accumulating the pulses generated by the processor into

internal 32-bit accumulation registers. The content of these

registers is transferred to the VA-hour registers, xVAHR[31:0],

when these registers are accessed. Figure 62 from the Active

Energy Calculation section illustrates this process. The

VATHR[47:0] 48-bit register contains the threshold. Its value

depends on how much energy is assigned to one LSB of the

VA-hour registers. Supposing a derivative of apparent energy

(VAh) of [10n VAh], where n is an integer, is desired as one LSB

of the xVAHR register, then, the xVATHR register can be

computed using the following equation:

PMAX

VATHR

3600

where:

PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power

computed when the ADC inputs are at full scale.

fS = 8 kHz, the frequency with which the DSP computes the

instantaneous power.

UFS, IFS are the rms values of the phase voltages and currents

when the ADC inputs are at full scale.

VATHR[47:0] is a 48-bit register. As previously stated, the serial

ports of the ADE7878 work on 32-, 16-, or 8-bit words. Similar

to the WTHR[47:0] register presented in Figure 63, VATHR[47:0]

is accessed as two 32-bit registers (VATHR1[31:0] and

VATHR0[31:0]), each having eight MSBs padded with 0s.

This discrete time accumulation or summation is equivalent to

integration in continuous time following the description in

Equation 44.

()

⎭

⎬

⎫

⎩

⎨

⎧

∑

∫

∞

→

Lim

ergy

ApparentEn

(44)

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