ADE7878 datasheet(44/92 Pages) AD

44 / 92 page

ADE7878

Rev. 0 | Page 44 of 92

dEnergy

Power =

(23)

Bits[8:6] (REVAPC, REVAPB, and REVAPA, respectively) in the

STATUS0[31:0] register are set when a sign change occurs in the

power selected by Bit 6 (REVAPSEL) in the ACCMODE[7:0]

Conversely, energy is given as the integral of power, as follows:

()dt

Energy

∫

(24)

Bits[2:0] (CWSIGN, BWSIGN, and AWSIGN, respectively) in

the PHSIGN[15:0] register are set simultaneously with the

REVAPC, REVAPB, and REVAPA bits. They indicate the sign of

the power. When they are 0, the corresponding power is positive.

When they are 1, the corresponding power is negative.

Total and fundamental active energy accumulations are always

signed operations. Negative energy is subtracted from the active

energy contents.

The ADE7878 achieves the integration of the active power

signal in two stages (see Figure 61). The process is identical for

both total and fundamental active powers. The first stage is

accomplished inside the DSP: every 125 μs (8 kHz frequency),

the instantaneous phase total or fundamental active power is

accumulated into an internal register. When a threshold is

reached, a pulse is generated at the processor port and the

threshold is subtracted from the internal register. The sign of

the energy in this moment is considered the sign of the active

power (see Sign of Active Power Calculation section for details).

The second stage is done outside the DSP and consists of

accumulating the pulses generated by the processor into internal

32-bit accumulation registers. The content of these registers is

transferred to the watt-hour registers, xWATTHR[31:0] and

xFWATTHR[31:0], when these registers are accessed.

Bit REVAPx of the STATUS0[31:0] register and Bit xWSIGN in the

PHSIGN[15:0] register refer to the total active power of Phase x,

the power type being selected by Bit 6 (REVAPSEL) in the

ACCMODE[7:0] register.

Interrupts attached to Bits[8:6] (REVAPC, REVAPB, and

REVAPA, respectively) in the STATUS0[31:0] register can be

enabled by setting Bits[8:6] in the MASK0[31:0] register. If

enabled, the IRQ0 pin is set low and the status bit is set to 1

whenever a change of sign occurs. To find the phase that

triggered the interrupt, the PHSIGN[15:0] register is read

immediately after reading the STATUS0[31:0] register. Next, the

status bit is cleared and the IRQ0 pin is returned to high by writing

to the STATUS0 register with the corresponding bit set to 1.

Active Energy Calculation

As previously stated, power is defined as the rate of energy flow.

This relationship can be expressed mathematically as

AVGAIN

HPFDIS

[23:0]

HPF

AIGAIN

HPFDIS

[23:0]

DIGITAL

INTEGRATOR

REVAPA BIT IN

STATUS0[31:0]

HPF

AWGAIN

AWATTOS

APHCAL

ACCUMULATOR

WTHR[47:0]

AWATTHR[31:0]

32-BIT

LPF2

DIGITAL SIGNAL PROCESSOR

Figure 61. Total Active Energy Accumulation

ADE7878 数据表(PDF) 44 Page - Analog Devices

ADE7878 数据表(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载