ADE7878 datasheet(33/92 Pages) AD

33 / 92 page

ADE7878

Rev. 0 | Page 33 of 92

When the Phase B voltage falls below the indicated threshold

into the SAGLVL[23:0] register for two line cycles, Bit

VSPHASE[1] in the PHSTATUS[15:0] register is set to 1, and Bit

VSPHASE[0] is cleared to 0. Simultaneously, Bit 16 (sag) in the

STATUS1[31:0] register is set to 1 to indicate the condition.

Note that the internal zero-crossing counter is always active. By

setting the SAGLVL[23:0] register, the first SAG detection

result is, therefore, not executed across a full SAGCYC period.

Writing to the SAGCYC[7:0] register when the SAGLVL[23:0]

is already initialized resets the zero-crossing counter, thus

ensuring that the first SAG detection result is obtained across a

full SAGCYC period.

The recommended procedure to manage SAG events is the

following:

Enable SAG interrupts in the MASK1[31:0] register by

setting Bit 16 (SAG) to 1.

When a SAG event happens, the IRQ1 interrupt pin goes

low and Bit 16 (SAG) in the STATUS1[31:0] is set to 1.

The STATUS1[31:0] register is read with Bit 16 (sag) set to 1.

PHSTATUS[15:0] is read, identifying on which phase or

phases a SAG event happened.

The STATUS1[31:0] register is written with Bit 16 (SAG)

set to 1. Immediately, the SAG bit and all Bits[14:12]

(VSPHASE[2:0]) of the PHSTATUS[15:0] register are

erased.

Sag Level Set

The content of the SAGLVL[23:0] SAG level register is

compared to the absolute value of the output from HPF. Writing

5,928,256 (0x5A7540) to the SAGLVL register, puts the SAG

detection level at full scale (see the Voltage Channel ADC

section), thus; the SAG event is triggered continuously. Writing

0x00 or 0x01 puts the SAG detection level at 0, therefore, the

SAG event is never triggered.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words. Similar to the register presented in

Figure 33, the SAGLVL register is accessed as a 32-bit register

with eight MSBs padded with 0s.

Peak Detection

The ADE7878 records the maximum absolute values reached by

the voltage and current channels over a certain number of half-

line cycles and stores them into the less significant 24 bits of the

VPEAK[31:0] and IPEAK[31:0] 32-bit registers.

The PEAKCYC[7:0] register contains the number of half-line

cycles used as a time base for the measurement. The circuit uses

the zero-crossing points identified by the zero-crossing detection

circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE[7:0] register

select the phases upon which the peak measurement is performed.

Bit 2 selects Phase A, Bit 3 selects Phase B, and Bit 4 selects

Phase C. Selecting more than one phase to monitor the peak

values decreases proportionally the measurement period indi-

cated in the PEAKCYC[7:0] register because zero crossings

from more phases are involved in the process. When a new

peak value is determined, one of Bits[26:24] (IPPHASE[2:0] or

VPPHASE[2:0]) in the IPEAK[31:0] and VPEAK[31:0] registers

is set to 1, identifying the phase that triggered the peak detection

event. For example, if a peak value has been identified on Phase

A current, Bit 24 (IPPHASE[0]) in the IPEAK[31:0] register is

set to 1. If next time a new peak value is measured on Phase B,

then Bit 24 (IPPHASE[0]) of the IPEAK[31:0] register is cleared

to 0, and Bit 25 (IPPHASE[1]) of the IPEAK[31:0] register is set

to 1. Figure 47 shows the composition of the IPEAK and VPEAK

registers.

PEAK DETECTED

ON PHASE C

00000

27 26 25 24 23

24 BIT UNSIGNED NUMBER

PEAK DETECTED

ON PHASE A

IPPHASE/VPPHASE BITS

PEAK DETECTED

ON PHASE B

Figure 47. Composition of IPEAK[31:0] and VPEAK[31:0] Registers

PHASE A

CURRENT

PHASE B

CURRENT

BIT 24

OF IPEAK

BIT 25

OF IPEAK

PEAK VALUE WRITTEN INTO

IPEAK AT THE END OF FIRST

PEAKCYC PERIOD

END OF FIRST

PEAKCYC = 16 PERIOD

BIT 24 OF IPEAK

CLEARED TO 0 AT

THE END OF SECOND

PEAKCYC PERIOD

BIT 25 OF IPEAK

SET TO 1 AT THE

END OF SECOND

PEAKCYC PERIOD

END OF SECOND

PEAKCYC = 16 PERIOD

PEAK VALUE WRITTEN INTO

IPEAK AT THE END OF SECOND

PEAKCYC PERIOD

Figure 48. Peak Level Detection

Figure 48 shows how the ADE7878 records the peak value on

the current channel when measurements on Phase A and Phase B

are enabled (Bit PEAKSEL[2:0] in MMODE[7:0] are 011).

PEAKCYC[7:0] is set to 16, meaning that the peak measure-

ment cycle is four line periods. The maximum absolute value

of Phase A is the greatest during the first four line periods

(PEAKCYC = 16); therefore, the maximum absolute value is

written into the less significant 24 bits of the IPEAK[31:0]

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