ADE7878 datasheet(25/92 Pages) AD

25 / 92 page

ADE7878

Rev. 0 | Page 25 of 92

The Σ-Δ converter uses two techniques to achieve high resolu-

tion from what is essentially a 1-bit conversion technique. The

first is oversampling. Oversampling means that the signal is

sampled at a rate (frequency) that is many times higher than

the bandwidth of interest. For example, the sampling rate in

the ADE7878 is 1.024 MHz, and the bandwidth of interest is

40 Hz to 2 kHz. Oversampling has the effect of spreading the

quantization noise (noise due to sampling) over a wider band-

width. With the noise spread more thinly over a wider bandwidth,

the quantization noise in the band of interest is lowered, as

shown in Figure 28. However, oversampling alone is not efficient

enough to improve the signal-to-noise ratio (SNR) in the band

of interest. For example, an oversampling ratio of 4 is required

just to increase the SNR by only 6 dB (1 bit). To keep the over-

sampling ratio at a reasonable level, it is possible to shape the

quantization noise so that the majority of the noise lies at the

higher frequencies. In the Σ-Δ modulator, the noise is shaped

by the integrator, which has a high-pass-type response for the

quantization noise. This is the second technique used to achieve

high resolution. The result is that most of the noise is at the

higher frequencies where it can be removed by the digital low-

pass filter. This noise shaping is shown in Figure 28.

NOISE

SIGNAL

NOISE

SIGNAL

2 4

512

FREQUENCY (kHz)

HIGH RESOLUTION

OUTPUT FROM

DIGITAL LPF

1024

2 4

512

FREQUENCY (kHz)

1024

DIGITAL FILTER

SHAPED NOISE

ANTIALIAS FILTER

(RC)

SAMPLING

FREQUENCY

Figure 28. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

Antialiasing Filter

Figure 27 also shows an analog low-pass filter (RC) on the input

to the ADC. This filter is placed outside the ADE7878, and its

role is to prevent aliasing. Aliasing is an artifact of all sampled

systems and is illustrated in Figure 29. Aliasing means that

frequency components in the input signal to the ADC, which

are higher than half the sampling rate of the ADC, appear in the

sampled signal at a frequency below half the sampling rate.

Frequency components above half the sampling frequency (also

known as the Nyquist frequency, that is, 512 kHz) are imaged or

folded back down below 512 kHz. This happens with all ADCs

regardless of the architecture. In the example shown, only

frequencies near the sampling frequency, that is, 1.024 MHz,

move into the band of interest for metering, that is, 40 Hz to

2 kHz. To attenuate the high frequency (near 1.024 MHz) noise

and prevent the distortion of the band of interest, a low-pass

filer (LPF) must be introduced. For conventional current

sensors, it is recommended to use one RC filter with a corner

frequency of 5 kHz for the attenuation to be sufficiently high at

the sampling frequency of 1.024 MHz. The 20 dB per decade

attenuation of this filter is usually sufficient to eliminate the

effects of aliasing for conventional current sensors. However, for a

di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per

decade gain. This neutralizes the 20 dB per decade attenuation

produced by the LPF. Therefore, when using a di/dt sensor, take

care to offset the 20 dB per decade gain. One simple approach is

to cascade one additional RC filter; thus, a −40 dB per decade

attenuation is produced.

ALIASING EFFECTS

SAMPLING

FREQUENCY

IMAGE

FREQUENCIES

512

FREQUENCY (kHz)

1024

Figure 29. Aliasing Effects

ADC Transfer Function

All ADCs in the ADE7878 are designed to produce the same

24-bit signed output code for the same input signal level. With a

full-scale input signal of 0.5 V and an internal reference of 1.2 V,

the ADC output code is nominally 5,928,256 (0x5A7540). The

code from the ADC may vary between 0x800000 (−8,388,608)

and 0x7FFFFF (+8,388,607); this is equivalent to an input signal

level of ±0.707 V. However, for specified performance, it is

recommended not to exceed the nominal range of ±0.5 V. The

ADC performance is guaranteed only for input signals lower

than ±0.5 V.

CURRENT CHANNEL ADC

Figure 30 shows the ADC and signal processing path for

Input IA of the current channels (it is the same for IB and IC).

The ADC outputs are signed twos complement 24-bit data-

words and are available at a rate of 8 kSPS (thousand samples

per second). With the specified full-scale analog input signal

of ±0.5 V, the ADC produces its maximum output code value.

Figure 30 shows a full-scale voltage signal applied to the differ-

ential inputs (IAP and IAN). The ADC output swings between

−5,928,256 (0xA58AC0) and +5,928,256 (0x5A7540). The

input, IN, corresponds to the neutral current of a 3-phase

system. If no neutral line is present, then connect this input to

AGND. The datapath of the neutral current is similar to the

path of the phase currents and is presented in Figure 31.

ADE7878 数据表(PDF) 25 Page - Analog Devices

ADE7878 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载

链接网址

ADE7878 数据表(PDF) 25 Page - Analog Devices

ADE7878 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表 下载

链接网址

数据表下载