ADE7878 datasheet(32/92 Pages) AD

32 / 92 page

ADE7878

Rev. 0 | Page 32 of 92

The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit

unsigned registers with 1 LSB corresponding to 3.90625 μs

(256 kHz clock), which means a resolution of 0.0703° (360° ×

50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° ×

60 Hz/256 kHz) for 60 Hz systems. The delays between phase

voltages or phase currents are used to characterize how

balanced the load is. The delays between phase voltages and

currents are used to compute the power factor on each phase as

shown in the following Equation 5:

cosφx = cos

⎥

⎦

⎤

⎢

⎣

⎡

kHz

256

360

LINE

ANGLEx

(5)

where x = A, B, or C and fLINE is 50 Hz or 60 Hz.

Period Measurement

The ADE7878 provides the period measurement of the line in

the voltage channel. Bits[1:0] (PERSEL[1:0]) in the MMODE[7:0]

period register is a 16-bit unsigned register and is updated every

line period. Because of the LPF1 filter (see Figure 40), a settling

time of 30 ms to 40 ms is associated with this filter before the

measurement is stable.

The period measurement has a resolution of 3.90625 μs/LSB

(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)

when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)

when the line frequency is 60 Hz. The value of the period register

for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and

for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The

length of the register enables the measurement of line frequencies

as low as 3.9 Hz (256 kHz/216). The period register is stable at

±1 LSB when the line is established and the measurement does

not change.

The following expressions can be used to compute the line

period and frequency using the Period[15:0] register:

[]

sec

256

]

[

Period

L =

(6)

]

[

]

[

256

Period

L =

(7)

Phase Voltage Sag Detection

The ADE7878 can be programmed to detect when the absolute

value of any phase voltage drops below a certain peak value for a

number of half-line cycles. The phase where this event took place is

identified in Bits[14:12] (VSPHASE[2:0]) of the PHSTATUS[15:0]

PHASE A VOLTAGE

BIT 16 (SAG) IN

STATUS1[31:0]

VSPHASE[0] =

PHSTATUS[12]

IRQ1 PIN

FULL SCALE

SAGLVL[23:0]

FULL SCALE

SAGLVL[23:0]

SAGCYC[7:0] = 0x4

PHASE B VOLTAGE

VSPHASE[1] =

PHSTATUS[13]

STATUS[16] AND

PHSTATUS[13]

SET TO 1

STATUS1[16] AND

PHSTATUS[12]

CANCELLED BY A

WRITE TO

STATUS1[31:0]

WITH SAG BIT SET

SAGCYC[7:0] = 0x4

Figure 46. Sag Detection

Figure 46 shows Phase A voltage falling below a threshold that is

set in the SAG level register (SAGLVL[23:0]) for four half-line

cycles (SAGCYC = 4). When Bit 16 (SAG) in the STATUS1[31:0]

the PHSTATUS[15:0] register is also set to 1 because the event

happened on Phase A. Bit 16 (SAG) in the STATUS1[31:0] reg-

ister, and all Bits[14:12] (VSPHASE[2:0]) of the PHSTATUS[15:0]

STATUS1[31:0] register with the SAG bit set to 1.

The SAGCYC[7:0] register represents the number of half-line

cycles the phase voltage must remain below the level indicated

in the SAGLVL register to trigger a SAG condition; 0 is not a

valid number for SAGCYC. For example, when the SAG cycle

(SAGCYC[7:0]) contains 0x07, the SAG flag in the STATUS1[31:0]

the line voltage falls below the threshold. If Bit 16 (SAG) in

MASK1[31:0] is set, the IRQ1 interrupt pin is driven low in case

of a SAG event in the same moment the Status Bit 16 (SAG) in

STATUS1[31:0] register is set to 1. The SAG status bit in the

STATUS1[31:0] register and all Bits[14:12] (VSPHASE[2:0]) of

the PHSTATUS[15:0] register are cleared, and the IRQ1 pin is

returned to high by writing to the STATUS1[31:0] register with

the status bit set to 1.

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