ADE7878 datasheet(21/92 Pages) AD

21 / 92 page

ADE7878

Rev. 0 | Page 21 of 92

Only a power-down or setting the RESET pin low can reset the

ADE7878 to use the I2C port. Once locked, the serial port choice is

maintained when the ADE7878 changes PSMx power modes.

Immediately after entering PSM0, theADE7878 sets all regis-

ters to their default values, including CONFIG2[7:0] and

LPOILVL[7:0].

The ADE7878 signals the end of the transition period by

triggering the IRQ1 interrupt pin low and setting Bit 15

(RSTDONE) in the STATUS1[31:0] register to 1. This bit is

0 during the transition period and becomes 1 when the tran-

sition ends. The status bit is cleared and the IRQ1 pin is returned

high by writing the STATUS1[31:0] register with the corresponding

bit set to 1. Because the RSTDONE is an unmaskable interrupt,

Bit 15 (RSTDONE) in the STATUS1[31:0] register must be

cancelled for the IRQ1 pin to return high. It is recommended

to wait until the IRQ1 pin goes low before accessing the

STATUS1[31:0] register to test the state of the RSTDONE bit.

At this point, as a good programming practice, it is also

recommended to cancel all other status flags in the

STATUS1[31:0] and STATUS0[31:0] registers by writing

the corresponding bits with 1.

Initially, the DSP is in idle mode, which means it does not

execute any instruction. This is the moment to initialize all

ADE7878 registers and then write 0x0001 into the Run[15:0]

section for details on the Run[15:0] register).

If the supply voltage, VDD, drops lower than 2 V ± 10%, the

ADE7878 enters an inactive state, which means that no

measurements and computations are executed.

HARDWARE RESET

The ADE7878 has a RESET pin. If the ADE7878 is in PSM0

mode and the RESET pin is set low, then the ADE7878 enters

the hardware reset state. The ADE7878 must be in PSM0 mode

for a hardware reset to be considered. Setting the RESET pin

low while the ADE7878 is in PSM1, PSM2, and PSM3 modes

does not have any effect.

If the ADE7878 is in PSM0 mode and the RESET pin is toggled

from high to low and then back to high after at least 10 μs, all the

registers are set to their default values, including CONFIG2[7:0]

and LPOILVL[7:0]. The ADE7878 signals the end of the transi-

tion period by triggering the IRQ1 interrupt pin low and setting

Bit 15 (RSTDONE) in the STATUS1[31:0] register to 1. This bit

is 0 during the transition period and becomes 1 when the tran-

sition ends. The status bit is cleared and the IRQ1 pin is

returned high by writing to the STATUS1[31:0] register with

the corresponding bit set to 1.

After a hardware reset, the DSP is in idle mode, which means it

does not execute any instruction.

Because the I2C port is the default serial port of theADE7878, it

becomes active after a reset state. If SPI is the port used by the

external microprocessor, the procedure to enable it must be

repeated immediately after the RESET pin is toggled back to

high (see the

section for details).

Serial Interfaces

At this point, it is recommended to initialize all of the ADE7878

registers and then write 0x0001 into the Run[15:0] register to

start the DSP. See the Digital Signal Processor section for details

on the Run[15:0] register.

SOFTWARE RESET FUNCTIONALITY

Bit 7 (SWRST) in the CONFIG[15:0] register manages the soft-

ware reset functionality in PSM0 mode. The default value of this

bit is 0. If this bit is set to 1, then the ADE7878 enters a software

reset state. In this state, almost all internal registers are set to

their default values. In addition, the choice of what serial port,

I2C or SPI, is in use remains unchanged if the lock-in procedure

has been previously executed (see the Serial Interfaces for details).

The registers that maintain their values despite the SWRST bit

being set to 1 are CONFIG2[7:0] and LPOILVL[7:0]. When the

software reset ends, Bit 7 (SWRST) in CONFIG[15:0] is cleared

to 0, the IRQ1 interrupt pin is set low, and Bit 15 (RSTDONE)

in the STATUS1[31:0] register is set to 1. This bit is 0 during the

transition period and becomes 1 when the transition ends. The

status bit is cleared and the IRQ1 pin is set back high by writing to

the STATUS1[31:0] register with the corresponding bit set to 1.

After a software reset ends, the DSP is in idle mode, which

means it does not execute any instruction. It is recommended

to initialize all the ADE7878 registers and then write 0x0001

into the Run[15:0] register to start the DSP (see the Digital

Signal Processor section for details on the Run[15:0] register).

Software reset functionality is not available in PSM1, PSM2, or

PSM3 mode.

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