PC87570-ICCSLASHVUL datasheet(22/168 Pages) NSC

22 / 168 page

Signal/Pin Connection and Description

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CLK

107

PC87570 internal clock (On-chip Clock Multi-

plier output). Available in all environments. For

IRE environment, set MCFG.CLKOE=1. See

Table 2-5 on page 27.

D15-0

138-123

152-137

TTL

CR16A Memory Data bus bits 15 through 0.

DA3-0

88-85

98-95

ANOUT

Digital to Analog Converter Output.

ENV1,0

93, 94

103, 104

STRAP

Environment select strap pins.These pins deﬁne

if the device environment, IRE, IRD or DEV.

They are sampled on power-up reset. See Sec-

tion 2.4 on page 26.

EXINT0

EXINT10

EXINT11

EXINT15

TTL

External Interrupt Inputs 0, 10, 11, 15. Interrupt

signals for general purpose use. These interrupt

signals are asynchronous. See Table 9-2 on

page 82.

GA20

Gate A20 output. See Section 5.11.6 on page

54.

GND

22, 24,

60, 99,

146

24, 26,

66, 109,

160

N/A

Ground for both on-chip logic, output drivers

and back-up battery circuit. See Figure 19-1 on

page 132 for details on connections with

AGND. See also Figure 16-4 on page 125 and

Figure 17-2 on page 129.

HA18-0

10-1,

160-152

12-3,

174-166

TTL

Host Address lines inputs to address registers

in the KBC, PM, RTC/APC and the conﬁgura-

tion registers. See Section 5.5.2 on page 50

and Section 5.4.3 on page 50. See also

“HPWRON” pin description below.

HAEN

TTL

Host Address Enable should be low during

HIORD and HIOWR bus transactions, otherwise

the bus transaction is ignored. Refer to Section

19.5.4 on page 150.

HD7-0

20-13

22-15

TTL

CMHD2

Host Data. Bi-directional data bus used to inter-

face the PC87570 to the peripheral data bus of

the host. Refer to Section 19.5.4 on page 150.

HDEN

101

111

STRAP

Host Device Enable, strap pin.

When pulled high during power-up reset, con-

ﬁgures the Host device (host interface and

RTC) to be enabled as default after each reset.

When low during power-up reset, the mother-

board PnP protocol must be used to enable the

host access to these devices after each reset.

See Section 2.4.2 on page 26 and Section

5.11.5 on page 54.

HIOCHRDY

OD2

Host I/O Channel Ready. An open drain output

that enables extending the host access. This is

used for handling the dual ported access to the

CMOS RAM and to share memory with the

host.

See

“HRMS”

and

“HPWRON”

pins

description below.

HIOR

144

158

TTL

Host I/O Read. Active-low input that signals an

I/O data read by the host processor.

Signal

Pin Number

Buffer Type

Function

160-pin

176-pin

Input

Output

PC87570-ICC/VUL 数据表(PDF) 22 Page - National Semiconductor (TI)

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