PC87570-ICCSLASHVUL datasheet(66/168 Pages) NSC

66 / 168 page

Real-Time Clock (RTC) and Advanced Power Control (APC)

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Figure 6-3. Divider Chain Control

Bits 6-4 (DV2-0) of the CRA Register control the following

functions:

Normal operation of the divider chain (counting)

Divider chain reset to 0

Bank selection scheme

Oscillator activity when only VBAT power is present

(backup state).

The divider chain can be activated by setting normal opera-

tional mode (bits 6-4 of CRA = 01X or 100). The first update

occurs 500 ms after divider chain activation.

Bits 3-0 of the CRA Register select one the of fifteen taps

from the divider chain to be used as a periodic interrupt. The

periodic flag becomes active after half of the programmed

period has elapsed, following divider chain activation.

See Section 6.3.1 on page 69 for more details.

6.2.9

Timekeeping

Data Format

Time is kept in BCD or binary format, as determined by bit

2 (DM) of Control Register B (CRB), and in either 12 or 24-

hour format, as determined by bit 1 of this register.

Note: When changing the above formats, re-initialize all

the time registers.

Daylight Saving

Daylight saving time exceptions are handled automatically,

as described in "Bit 0 - Daylight Saving Enable (DSE)" on

page 70.

Leap Years

Leap year exceptions are handled automatically by the in-

ternal calendar function. Every four years, February is ex-

tended to 29 days. Year 2000 is a leap year.

6.2.10

Updating

The time and calendar registers are updated once per sec-

ond regardless of bit 7 (SET) of the CRB Register. Since the

time and calendar registers are updated serially, unpredict-

able results may occur if they are accessed during the up-

date. Therefore, you must ensure that reading or writing to

the time storage locations does not coincide with a system

update of these locations. There are several methods to

avoid this contention.

Method 1

1. Set bit 7 of the CRB Register to 1. This takes a “snap-

shot” of the internal time registers and loads them into

the user copy registers. The user copy registers are

seen when accessing the RTC from outside, and are

part of the double buffering mechanism. You may keep

this bit set for up to 1 second, since the time/calendar

chain continue to be updated once per second.

2. Read or write the required registers (since bit 1 is set,

you will be accessing the user copy registers). If you

perform a read operation, the information you read is

correct from the time when bit 1 was set. If you perform

a write operation, you will write only to the user copy

registers.

3. Reset bit 1 to 0. During the transition, the user copy reg-

isters update the internal registers, using the double

buffering mechanism to ensure that the update is per-

formed between two time updates. This mechanism en-

ables new time parameters to be loaded in the RTC.

Method 2

1. Access the RTC registers after detection of an Update

Ended interrupt. This implies that an update has just

been completed and 999 ms remain until the next up-

date.

2. To detect an Update Ended interrupt, you may either:

Poll bit 4 (UF) of Control Register C (CRC)

b. Use the following interrupt routine:

— Set bit 4 (UIE) of the CRB Register.

— Wait for an interrupt from IRQ8 pin.

— Clear the IRQF ﬂag of the CRC Register before

exiting the interrupt routine.

Method 3

Poll bit 7 (UIP) of the CRA Register. The update occurs

244

µs after this bit goes high. Therefore, if a 0 is read, the

time registers will remain stable for at least 244

µs.

Method 4

Use a periodic interrupt routine to determine if an update cy-

cle is in progress, as follows:

1. Set the periodic interrupt to the desired period.

2. Set bit 6 (PIE) of the CRB Register to enable the inter-

rupt from periodic interrupt.

3. Wait for the periodic interrupt appearance. This indi-

cates that the period represented by the following ex-

pression remains until another update occurs:

[(Period of periodic interrupt

/ 2) + 244 µs]

32.768 KHz

1Hz

Divider Chain

DV2 DV1 DV0

CRA Register

Osc

Enable

Bank

Select

32KX1

32KX2

To other

Reset

modules

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