PC87570-ICCSLASHVUL datasheet(77/168 Pages) NSC

77 / 168 page

High Frequency Clock Generator (HFCG)

www.national.com

7.2.2

Fast Clock Setting

The HFCG maintains an internal 14-bit HFCGI variable.

The HFCGI variable is defined by two byte-wide registers:

HFCGIL and HFCGIH. If new HFCGM and HFCGN values

are loaded, the frequency multiplier automatically searches

for the HFCGI value needed to lock onto the target frequen-

cy. The locking process can take up to several milliseconds

to complete. The HFCGI variable can be recorded for a giv-

en HFCGM and HFCGN set of values and used later to re-

duce the time needed for frequency locking.

To record the HFCGI value:

1. Read the HFCGIL value.

2. Check if the IVLID bit in the HFCGCTRL Register is set

to 0. If yes, repeat stages 1 and 2.

3. Read the HFCGIH value.

To fast load a new setting, load the HFCGM and HFCGN

values, and the corresponding HFCGI value. Then set the

FAST bit in the HFCGCTRL Register to 1; the frequency

multiplier quickly locks onto the target frequency without

searching for a new HFCGI value.

To fast set a new clock frequency:

1. Write the HFCGN value.

2. Write the HFCGML value.

3. Write the HFCGMH value.

4. Write the HFCGIL value.

5. Write the HFCGIH value.

6. Set the FAST bit in the HFCGCTRL Register to 1.

Changes in temperature or voltage may cause variations in

the value of HFCGI for a given output frequency. If these

changes occur in the interval between recording the HFCGI

to its use, the output frequency generated following a fast

frequency setting may differ from the target frequency.

However, after some time, the output frequency converges

to the desired frequency.

7.3

HFCG REGISTERS

7.3.1

HFCG Control Register (HFCGCTRL)

The HFCGCTRL Register is a byte-wide, read/write register

that sets the frequency multiplier’s operating parameters.

Upon power-up and WATCHDOG reset, bits 0 through 3

are initialized to Ch.

Bit 0 - Load M and N Values (LOAD)

Write 1 to the LOAD bit to perform a normal frequency

change by loading the HFCGML, HFCGMH and

HFCGN buffer data to the frequency multiplier. The bit

always reads back as 0. LOAD must be cleared (0)

when FAST bit is set.

Bit 1 - Load M, N and I Values (FAST)

Write 1 to the FAST bit to perform a fast frequency

change by loading the HFCGML, HFCGMH, HFCGN,

HFCGIH and HFCGIL input buffer data in the frequency

multiplier. The bit always reads back 0. FAST must be

cleared (0) when LOAD is set.

Bit 2 - Multiplier Enable (ENABLE)

ENABLE is a read only bit. It provides the status of the PMC

enable/disable command. Any data written to this bit is

ignored.

0: Disabled

1: Enabled

Bit 3 - Output Clock Status (OHFC)

OHFC is a read only bit. It indicates when the HFCG is

oscillating and produces a stable clock. Any data written

to this bit is ignored.

0: Not oscillating

1: Oscillating with stable output

Bit 4 - I Value Valid (IVLID)

IVLID is a read only bit; data written to it is ignored. This

bit has meaning only after the ﬁrst read from the

HFCGIL Register.

0: Data read is invalid; repeat HFCGIL Register read

operation

1: Data read is valid; HFCGIH can be read

7.3.2

HFCGM Low Value Register (HFCGML)

The HFCGML Register is a byte-wide, read/write register

containing the lower eight bits of the frequency multiplier

HFCGM value. Data written to the register is stored in the

setup buffer. Reading the register returnees the current sta-

tus of the frequency set registers. Upon power-up and

WATCHDOG reset it is loaded with C5h.

7.3.3

HFCGM High Value Register (HFCGMH)

The HFCGMH Register is a byte-wide, read/write register

containing the upper six bits of the frequency multiplier

HFCGM value. Data written to the register is stored in the

setup buffer. Reading the register returns the current status

of the frequency set registers. Upon power-up and WATCH-

DOG reset, it is loaded with 04h.

7.3.4

HFCGN Value Register (HFCGN)

The HFCGN Register is a byte-wide, read/write register con-

taining five bits of the frequency multiplier HFCGN value. Data

written to the register is stored in the setup buffer. Reading the

ters. Upon power-up and WATCHDOG reset, it is loaded with

0Ah.

Res

IVLID

OHFC

ENABLE

FAST

LOAD

HFCGM7-0

6 5

Res

HFCGM13-8

Res

HFCGN4-0

PC87570-ICC/VUL 数据表(PDF) 77 Page - National Semiconductor (TI)

PC87570-ICC/VUL 数据表(HTML) 77 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载