PC87570-ICCSLASHVUL datasheet(72/168 Pages) NSC

72 / 168 page

Real-Time Clock (RTC) and Advanced Power Control (APC)

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Power On

This is the normal state when the PC87570 is powered on.

This state may be initiated by various events in addition to

physically switching the system on. The PC system and the

PC87570 device are powered by VCC.

Note: The APC does not function when the 32.768 KHz

oscillator is not running.

6.5.4

System Power Switching Logic

In the Power On state, the APC is powered by VCC. If VCC

falls to the level of VCCON, the APC enters the Power Off

state and switches to VBAT.

When power returns after power-off, the APC enables the

generation of an APC-ON interrupt after a delay of 1 sec-

ond.

If VBAT falls below VLOWBAT, the oscillator, timekeeping

functions and APC cease functioning.

If neither VCC or VBAT is available, the system goes to No

Power state. It is initialized when it leaves this state.

6.5.5

APC-ON/APC-OFF Interrupt Signals

The APC checks when activation conditions are met, and

generates the APC-ON/APC-OFF interrupt signals accord-

ingly. The APC-ON/APC-OFF interrupt signals are active-

high pulses.

APC-ON interrupt is generated, when:

• Time Match Enable bit (bit 0 of APCR2) is 1 and there is

a match between the RTC and the time specified in the

pre-determined date registers.

User software must ensure unused date/time fields are

coherent to ensure a reliable comparison of valid bits.

• RING Enable bit (bit 3 of APCR2) is 1 and one of the fol-

lowing occurs:

— Bit 2 of APCR2 is 0 and a high-to-low transition is de-

tected on the RING input pin.

— Bit 2 0f APCR2 is 1 and a train of pulses is detected

on the RING input pin.

APC-OFF interrupt is generated, when:

A 1 is written to Software Off Command bit (bit 5 of

APCR1).

6.5.6

Entering Power States

Power Up

When power is first applied to the RTC, the APC registers

are initialized to the default values defined in APCR1,

APCR2 and APSR. See Table 6-5. This situation is defined

by the appearance of VBAT or VCC with no previous power.

The APC powers-up when the RTC supply is applied from

any source. It is in Power On state only when VCC is ap-

plied.

Power Off

The APC is in Power Off state when it is powered by VBAT.

Upon entering Power Off state, the following occurs:

• The RING pin (for detecting telephone line incoming sig-

nals for fax, modem or voice communication) is masked

(high).

The signal remain masked until 1 second after exit from

Power Off state (i.e., 1 second after switching from VBAT

to VCC)..

When the 1 second delay expires, new events can gen-

erate the APC-ON interrupt. In addition, if a time match

occurs during Power Off, the APC “remembers” to send

an APC-ON interrupt.

In case Power Off was entered before a host Software

Off Command was executed, an APC-ON interrupt is

generated for RING and/or predetermined wake-up

match events detected prior to entering Power Off

state.

6.5.7

Predetermined Wake-Up

The second, minute and hour values of the pre-determined

wake-up times are contained in the Seconds Alarm, Minutes

Alarm and Hours Alarm registers respectively (register off-

sets 01, 03 and 05 in all banks). The Day of Week, Date of

Month Month, Year and Century of the pre-determined date

is held in Bank 2, registers, offsets 43h-46h and 48h. These

eight registers are compared with the Seconds, Minutes,

Hours, Day of Week, Date of Month, Month, Year and Cen-

tury registers correspondingly (register offsets 00, 02, 04, 06,

07, 08, 09 in all banks and register offset 48 in Bank 1).

6.5.8

Ring Signal Event

An incoming telephone call is an event that may generate

an APC-ON interrupt in order to deal with a pending incom-

ing voice, fax or modem communication.

The PC87570 can detect a RING pulse falling edge, or a

RING pulse train with a frequency of at least 16 Hz that lasts

at least 0.19 seconds.

When APCR2.RPTDM is set, the APC is in a RING pulse

train detection mode and the existence of falling edges on

RING is monitored in time slots of 62.5 ms (16 Hz cycle

time). A RING pulse train detect event occurs if falling

edge(s) of RING are detected in three consecutive time

slots, following a time slot in which no falling edge of RING

is detected.

This method of detecting a RING pulse train filters out (does

not detect) a RING pulse train of less then 11 Hz, might de-

tect a RING pulse train of 11 Hz to 16 Hz, and guarantees

detection of a RING pulse train of at least 16 Hz.

If APCR2.RPTDM is cleared, a single falling edge on the

RING input will generate a RING wakeup event.

6.6

APC REGISTERS

The APC registers reside in the APC Bank 2 memory. The

RAM Lock register also resides in this bank. See Table 6-9

on page 75.

The APC control registers are not affected by system reset.

They are initialized to 0 only when power is applied for the

first time; i.e., application of either VBAT or VCC, when no

previous voltage is present.

Table 6-6. APC Control Registers

Offset

Mnemonic

40h

APCR1

APC Control Register 1

41h

APCR2

APC Control Register 2

42h

APSR

APC Status Register

47h

RLR

RAM Lock Register

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