PC87570-ICCSLASHVUL datasheet(100/168 Pages) NSC

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ACCESS.bus (ACB) Interface

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lem has occurred, it sends a negative acknowledge to

indicate that it can not accept additional data bytes.

13.2.6

Addressing Transfer Formats

Each device on the bus has a unique address. Before any

data is transmitted, the master transmits the address of the

slave being addressed. The slave device should send an

acknowledge signal on the SDA line, once it recognizes its

address.

The address consists of the first seven bits after a Start

Condition. The direction of the data transfer (R/W) depends

on the bit sent after the address - the eighth bit. A low-to-

high transition during a SCL high period indicates the Stop

Condition, and ends the transaction of SDA (Figure 13-5).

When the address is sent, each device in the system com-

pares this address with its own. If there is a match, the de-

vice considers itself addressed and sends an acknowledge

signal. Depending on the state of the R/W bit (1:read,

0:write), the device acts as a transmitter or a receiver.

The I2C bus protocol allows sending a general call address

to all slaves connected to the bus. The first byte sent spec-

ifies the general call address (00h) and the second byte

specifies the meaning of the general call (for example,

“Write slave address by software only”). Those slaves that

require the data acknowledge the call and become slave re-

ceivers; the other slaves ignore the call.

13.2.7

Arbitration on the Bus

Multiple master devices on the bus, require arbitration be-

tween their conflicting bus-access demands. Control of the

bus is initially determined according to address bits and

clock cycle. If the masters are trying to address the same

slave, data comparisons determine the outcome of this ar-

bitration. In master mode, the device immediately aborts a

transaction if the value sampled on the SDA line differs from

the value driven by the device. (An exception to this rule is

SDA while receiving data). In this cases the lines may be

driven low by the slave without causing an abort).

The SCL signal is monitored for clock synchronization and

to allow the slave to stall the bus. The actual clock period is

the one set by the master with the longest clock period or by

the slave stall period. The clock high period is determined

by the master with the shortest clock high period.

When an abort occurs during the address transmission, a

master that identifies the conflict, should give-up the bus

and switch to slave mode and continue to sample SDA to

see if it is being addressed by the winning master on the

bus.

13.3 FUNCTIONAL DESCRIPTION

The ACB module provides the physical layer for an AC-

CESS.bus compliant serial interface. The module is config-

urable as either a master or slave device. As a slave device,

the ACB module may issue a request to become the bus

master.

13.3.1

Master Mode

Requesting Bus Mastership

An ACCESS.bus transaction starts with a master device re-

questing bus mastership. It asserts a Start Condition, fol-

lowed by the address of the device it wants to access. If this

transaction is successfully completed, the software may as-

sume that the device has become the bus master.

For the device to become the bus master, the software

should perform the following steps:

Conﬁgure ACBCTL1.INTEN to the desired operation

mode (Polling or Interrupt) and Set ACBCTL1.START.

This causes the ACB to issue a Start Condition on the

ACCESS.bus, as soon as the ACCESS.bus is free

(ACBCST.BB=0 or other conditions that can delay

start). It then stalls the bus by holding SCL low.

If a bus conﬂict is detected, (i.e., some other device

pulls down the SCL signal before the PC87570 does),

ACBST.BER is set.

If there is no bus conﬂict, ACBST.MASTER and ACB-

ST.SDAST are set.

If ACBCTL1.INTEN is set, and either ACBST.BER or

ACBST.SDAST is set, an interrupt is sent to the

CR16A.

Sending the Address Byte

Once the PC87570 is the active master of the ACCESS.bus

(ACBST.MASTER is set), it can send the address on the

bus.

The address sent should not be the PC87570’s own ad-

dress, as defined in ACBADDR.ADDR, if ACBADDR.SAEN

is set, nor should it be the global call address if ACB-

ST.GMTCH.GMTCH is set.

To send the address byte use the following sequence:

For a receive transaction where the software requires

only one byte of data, it should set the ACBCTL1.ACK

bit. If only an address needs to be sent (for quick

Read/Write protocols, e.g.) or if the device requires

stall for some other reason, set the ACBCTL1.STAS-

TRE bit to 1.

Write the address byte (7-bit target device address),

and the direction bit, to the ACBSDA register. This

causes the module to generate a transaction. At the

end of this transaction, the acknowledge bit received is

copied to ACBST.NEGACK. During the transaction the

SDA and SCL lines are continuously checked for con-

ﬂict with other devices. If a conﬂict is detected, the

transaction is aborted, ACBST.BER is set, and ACB-

ST.MASTER is cleared.

If ACBCTL1.STASTRE is set and the transaction was

successfully completed (i.e., both ACBST.BER and

ACBST.NEGACK are cleared), ACBST.STASTR is set.

In this case, the ACB stalls any further ACCESS.bus

operations (i.e., holds SCL low). If ACBCTL1.INTEN is

set, it also sends an interrupt to the core.

If the requested direction is transmit, and the start

transaction was completed successfully (i.e., neither

ACBST.NEGACK nor ACBST.BER is set, and no other

master has accessed the device), ACBST.SDAST is

set to indicate that the module awaits attention.

If the requested direction is receive, the start transac-

tion was completed successfully and ACBCTL1.STAS-

TRE is cleared, the module starts receiving the ﬁrst

byte automatically.

Check that both ACBST.BER and ACBST.NEGACK

are cleared. If the ACBCTL1.INTEN bit is set, an inter-

rupt is generated when either ACBST.BER or ACB-

ST.NEGACK is set.

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